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Research On Flash Array Storage System

Posted on:2011-06-20Degree:MasterType:Thesis
Country:ChinaCandidate:W B LiFull Text:PDF
GTID:2178330338479870Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
As the latest developments in the field of high-speed and large-capacity storage, Flash Array storage system is developed with the semiconductor storage devices used broadly in Solid State Disk system design. Compared with Hard Disk Drive system, Flash array has the advantage of great shock resistance, reliability, high-heat and high-pressure resistance, etc, which brings strong adaptability to Flash Array system. Recently, along with improved demands for storage device in the fields of aerospace and military, Flash Array constituted by NAND Flash has been one of the most important storage methods in various major projects.Firstly, this thesis introduces the selection of Flash chips and gives the general framework of Flash Array module by the detailed comparison and analysis of NOR and NAND technologies. Furthermore, the design method of NAND Flash control core is presented by analyzing the performance of NAND Flash. On this basis, the paper gives detailed design ideas of controlling Flash Array by FPGA, which is divided into four modules by modularization design idea: Data buffer, Instruction decode, State machine and Muti-select. Besides, specific realization of blocks and interconnection between different blocks are explained in detail. ECC and bad block management section and the specific implementation of that are given through the study of bad block characteristics of Flash chip. Then, two algorithms Wear-Leveling and Garbage Collection are introduced, which can improve the performance of Flash chip. Based on the disadvantages of wear leveling in file systems, a synthesis algorithm combining the advantages of two algorithms is designed, and the implementation of that is given too.Finally, functions of Flash array are tested in the paper and synthesis algorithm compared with wear leveling in JFFS2 and YAFFS is also conducted. Experimental results show that the design of FPGA function module has rational structure, complete functions, meeting the time sequencing of Flash Array system. Synthesis algorithm can improve the shortage of wear leveling and inefficience of garbage collection in current file systems. Give a good reference for enhancing the reliability and service life of Flash chips.
Keywords/Search Tags:Flash Array, Bad Block Management, Wear-Leveling, Garabge-Collection
PDF Full Text Request
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