The Implementation Of RS Decoding Accelerator

The RS code is the most important and usual subclass of non-binary BCH code. As the RS code is effective in correcting random symbol errors and random burst-errors, it is widely used in communication and data storage systems for error control ranging from deep space communication to high density diskette. The cascade seeing the RS code as outer code and simple binary code as inner code could not only lower decoding complexity but also supply high data reliability.The paper makes the research based on EDA tools including ModelSim and Quartus 9.0. It designs the RTL codes and carries out simulation(including pre-simulation and post-simulation), test, verification and modularization designs. The whole structure is divided into five parts including syndromes calculation unit, error location polynomial calculation unit, error location searching unit, error values calculation unit and error modification unit.Then, BM algorithm for the RS code is analyzed and studied and the system structure diagram of the RS decoder is presented in the article. The paper implements the constrcution of Galois extension field and the process of syndromes calculation, error location polynomial calculation, error location calculation, and error values calculation. Then, the paper accomplishs the hardware design of the RS decoder, implements usual circuits for add and multiply algorithm in Galois extension field and presents the implemention circuits structure according to the computation and implemention method in every part of the whole structure. All the implemention circuit are presented in the following chapter. And then, input interface timing, output interface timing and some waveform signals are presented in the chapter. At last, the synthesis results are given. At last, we summarize the work we have done and make our expectation.