Missile-Borne Radar Signal Processing SoC Design

System on Chip (SoC) based on Application Specific Integrated Circuit (ASIC) can enhance the ability of the Integrated Circuit design by sufficiently utilizing the existing achievement. For the requirements of high speed, miniaturization and integration for Missile-Borne system, a schedule based on SoC technique for Missile-Borne radar signal processing is designed in the paper, which can reduce the cubage and the power, enhance the ability of detecting and tracking. Meanwhile, the chip has the functions that can be configured on hardware and programmed on software, which can satisfy the requirements of real-time system and multiple modes.Firstly, according to the kownledge of radar signal processing, we confirm the arithmetics in the SoC design. Secondly the selection and utilization of the FIR filters and the modules of FFT in the FPGA based on the techniques of IP reuse and verification of SoC are analyzed. By analyzing the influence of structure, speed, resources on power dissipation, the systolic filter and pipeline FFT are chosen to build the SoC system. Thirdly according to the knowledge of anti-radiation, the simulation of Triple Module Redundancy which used in the chip design is given based on FPGA. Finally, the logic design of signal processor based on advanced FPGA is accomplished according to the requirements of the Missle-Borne radar signal processing SoC. Meanwhile, the processing results of FPGA and the simulation results of MATLAB are compared and analyzed. The results indicate that the design requirements are satisfied in the system.