Research On Structure And Technology Of OLRDS

Chip reverse analysis is a powerful means to enhance the capacity of IC design. It is also an important way to keep information security out of the threat brought by the defects and vulnerability of chip. Off-line reverse analysis can analyze chip on high accuracy without special equipment and destroying the chip. So it is widely used to analyze programmable logic device. In this thesis, the study of OLRDS (Off-line Logic Reverse Data Sampling), which is the core of off-line reverse analysis, is specified. The space and time complexity of the data sampling algorithm without reset restriction is analyzed. The structure of state transition diagram and the search algorithm of path for driving state are improved.Major contributions and innovations endeavored in this thesis are as follows:1. By limiting the output condition of sequential logic circuit, the model of fathomable sequential machine is proposed. Based on the model, the abstractive description of data sampling algorithm is given. Then the feasibility of state drive by building full state transition diagram is proved.2. The factors influencing the speed of data sampling are analyzed from three aspects driving times, number of searching states and length of driving path. According to the analysis, the separate choose policy, improved breadth first search algorithm and the cycle tree structure is presented. The lay driving algorithm is raised on the cycle tree.3. Based on PC architecture, the OLRDS system is implemented. Meanwhile the three level data sampling model is raised. By building simulator of state transition diagram and off-line reverse analysis system, the performance of data sampling algorithms and the OLRDS system are test, by which the validity and rationality of the design of OLRDS system is confirmed.