Variable Fractional Delay FIR Digital Filter Design And Implementation On FPGA

Fractional delay FIR digital filters can change theirs delay parameters to make theirs frequency response different easily. So they are extremely useful in many domains. Such as timing adjustment, audio signal processing and speech coding and so on. But Fractional delay FIR digital filters are sensitive to theirs coefficients. And theirs coefficients are not symmetry. So, to implement same stage filters on hardware, Fractional delay FIR digital filters are more difficult than commonly FIR digital filters. So it is difficult to implement high stage Fractional delay FIR digital filters. This condition will be changed when FPGA is invented.FPGA is rich in logic resource. It is concurrent implementing program. So it adapts to design the digital FIR filters which are high granularity and parallel structure. You will change the program only to change the function of design. It is not necessary to design from zero again. And the module of the design can be used once more. So, not only the development time is short, the development cost is also low when design circuits on FPGA.The following works are carried out: at first, weighted least-squares method is used to design fractional delay FIR digital filter. In the design, filter coefficients are denoted as polynomial of fractional delay parameters. We make the matrix which is consisted of polynomial coefficients be a row so that be evaluated easily. Then we evaluate the objective error function with the closed-form integral. It is more accurate than the method which sums up a large number of discrete points value. Matrix Cholesky decomposition and adjusting the order of computation are used to avoid the ill-evaluation.Secondly, the distributed arithmetic and canonic signed digit encoding method are presented to design fractional delay filter. Multiplication operation is transformed to look-up table operation and combining with pipelining technology to reduce hardware resources using and improve processing speed, based on distributed arithmetic. Canonic signed digit encoding makes the zeros of the binary digital which express the coefficients of the filter most. That will reduce scale of hardware greatly and improve operation speed.At last, the design are synthesized and simulated through software Quartus II 7.1, and implemented on the aimed equipment which is produced by Altera company. Canonic signed digit encoding method consumes more logic resource than the distributed arithmetic method to design the fractional delay FIR filters. The maximal-frequency of the filters which are designed by Canonic signed digit encoding and distributed arithmetic method are 52.5MHz and 83.98MHz.The Weighted Least-Squares Method which is used to design fractional delay FIR digital filter is optimized. The designed filter is more accurate and lower complexity. The Canonic signed digit encoding and distributed arithmetic methods are used when implement the Fractional delay FIR digital filters in this paper. Some new approaches and methods are explored when design and implement the filter. These works are meaningful for theory and engineering.