Research On The Technology Of Non-preemptive Hardware Multithreading Applied In Network Processor

With the development of the technology of microelectronics and integrated circuit manufacturing techniques, the research on and design of Network processor architecture is moving in the direction of multi-core systems integration on chip. Programmable data processing unit with parallel multi-threaded structure has become a research focus of network processor data path processing because of its high efficiency and low power consumption.This paper focuses on multi-threaded processor architecture for low-cost hardware multi-threading technology. Through the use of explicit trigger hardware threads Triggered by the instruction to achieve the non-preemptive hardware threads switching and improve the efficiency of the processor's hardware threads trigger. By using the non-preemptive multi-threading technology based on the signal Wake-up mechanism, it can make each thread switching overhead reduce to zero overhead, and maximize the executive efficiency of each thread. By using the rotary-priority and signal wake-up mechanisms, they can minimize the delay of thread wake-up.The hardware multi-threaded processor designed in this paper is an improved processor based on a standard 5-stage pipeline RISC processor, by adding the main module of thread switching and associated registers to store the state and data; they can improve the data processing efficiency of the processor.The whole design is achieved by using the Verilog hardware description language, the parallel verification and performance analysis of the multi-threaded processor is completed on the FPGA platform.