Research On Optimizing The Characteristics Of 4H-SiC MESFET With Spacer And Field Plate

Silicon carbide (SiC) is a very promising candidate for high temperature, high power, high frequency, and radiation hardness applications because of its superior properties such as wide band gap, high critical breakdown field, high thermal conductivity and high saturation electron drift velocity. In recent years it became a hot research field of semiconductor. As the property of SiC material, now the high intrinsic surface states and interface states are prevalent in the successfully manufactured SiC microwave power MESFET devices, making the device output current decline sharply in DC characteristics .when devices is worked at high-frequency, current Instability and current collapse is caused by surface states and interface states. At present, the technologies of isolation layer and field plate are the main methods used to improve device performance. Isolation layer is used to suppress the surface traps, field plate is used to increase the breakdown voltage, both have very good results. However, no studies have yet to combine these two structures, allowed the device to suppress the surface traps for high output current and high breakdown voltage.To suppress the device performance degradation, the isolation layer and field plate are introduced at the same time. Not only achieved the inhibitory effect of surface traps but also the breakdown voltage is improved. By optimizing the parameters of the two structure, the device output current and breakdown voltage increase together. Firstly, 4H-SiC MESFET device structure and physical models is established by two-dimensional device simulator ISE-TCAD .According to the basic DC operating characteristics of traditional structure of 4H-SiC MESFET, research methods are determined through analysis of output characteristics, transfer characteristics and other characteristics. Secondly, the impact of the surface trap is studied from transfer characteristics and output characteristics , and find out the surface trap density and energy level that make the device performance degenerate mostly: density 1×10¹³cm^-2, energy level from the conduction band 1.8eV. In such cases, drain-source current of 4H-SiC MESFET is reduced by 120% , and the Tran conductance decrease by 50%. Third, on the basis of these studies, doping concentration ,depth and the depth of the buried gate of isolation layer were optimized by compare with the ideal trap-free condition .the optimal parameters: Spacer layer thickness:0.1μm, doping concentration 1×10¹⁴cm^-3, buried gate depth 0.05μm.Making simulation at this group of Optimization parameters, the surface trap effect has been effectively suppressed, and the introduction of small parasitic parameters, DC performance of device is greatly improved. Compared with the traditional structure of the trap, drain-source current increased by 130%, the Tran conductance gain of more than 20mS/mm voltage operating range increased by about 100%. Finally, a field plate is introduced on the isolation layer structure, and analysis the impact of the DC characteristics . By analyzing the mechanism of field plate , it's found that the field plate and isolated layers don't affect each other . Optimized field plate length, the breakdown voltage can be improved by 60%.