Research On Optimizing The Structure Of The Buried Gate-buried Channel 4H-SiC MESFET

SiC is a very promising candidate for high temperature, high power, high frequency, and radiation hardness applications because of its superior properties such as wide band gap, high critical breakdown field, high thermal conductivity and high saturation electron drift velocity. Therefore the power devices-Metal Semiconductor Field Effect Transistors (MESFETs) based on 4H-SiC have received increased attention. However, it has been found that surface trapping effects also play an important role in device instability.To solve this problem, some new structures were proposed, such as the buried-channe structure, the buried-gate structure and the buried gate-buried channel structure. In all of above structures, the buried gate-buried channel structure has the best electrical performances. Compared with normal structure, this structure consists of an n-buffer layer on the top of channel to form a"buried-channel"and a"buried-gate"structure where the activechannel is removed from the surface .By using this approach, the induced surface traps are physically removed from the channel region, such that the depletion depth caused by the unneutralized surface states can not reach the conductive channel.In order to get the better performances brought by this structure, we optimize this structure. Supposing the deepness of gate-buried is 0μm, we simulate the DC characteristics of the buried gate-buried channel 4H-SiC MESFETs with different thicknesses of n-buffer layer. We get the optimized thickness of n-buffer layer by analyzing the simulation results. Basing on the optimized thickness of n-buffer, we simulate the DC and AC characteristics of the buried gate-buried channel 4H-SiC MESFETs with different deepnesses of buried-gate,and get the the best deepness of buried-gate.