The Research Of Branch Prediction Of Superscalar Processor Based On Reuse Mechanism

In the past few decades, processors pipelined were designed deeper and wider for the demand of high-performance applications processors. However, because a large number of branch instructions were used in programming, and for the uncertainty implementation behavior, each branch instruction tends to bring a halt to wait for the process results, which seriously affected the implementation efficiency of processors. Therefore, the techniques of branch prediction had gradually been raised, and advanced branch prediction mechanism had also been gradually raised. How to improve branch prediction accuracy was a hot issue in the field experts.The last two years, foreign researchers and institutions began to study the data reuse technology in processor to solve the prediction accuracy issues of branch prediction. which main objective was how to reuse information of instruction and data redundancy to solve the problem of processor performance and power consumption. The results shown that reuse information not only increase accuracy of branch prediction, but also reduce the power consumption. The research results shown that the rationally utilized the techniques of data reuse not only improved the performance and reduced the power consumption of processor.The research and development trend of superscalar processors, branch prediction and the theory of data reuse were introduced in this paper. After configured the two dynamic branch prediction of GAs on 5 level superscalar SimpleScalar simulation platform, used of SimpleScalar tool procedures SPEC 95 benchmarks for comparative and analysis the experimental data, and found that those benchmarks certain amount of data can be reused, the general prediction recovery mechanism will lead to loss of a lot of clock cycles. Therefore, to solve the problem of above, this paper introduced a kind of Loop Detector and B-Cache, which were both based on the data reuse theory, then built the model of the new kind of superscalar processors. To verify the established model, analysis SimpleScalar source code, and modify the Sim_Outorder code. At the last achieved the B-Cache mechanism. The validation results showed that the Loop Detector could avoid duplication decoding to the large number of Loop program. The B-Cache made the recover just need only one clock cycle, which saved a lot of clock cycles.