A New Algorithm Based On Net Cratiality Judge Applying To FPGA Global Routing

A new kind of high-density ASIC ,eg. FPGA was emerged to cope with different users' defferent demands. High-density, high-speed, serized, small size, multi-function, low-power, cost-effectiveness, flexibilities in design are the most crucial characters of an FPGA. Also it developes rapidly throughout the world because it is limitless programmable .Now integrated circuit industry is progressing rapidly in deep sub-micron technology. This trend has put great challenges for the recently available tools of electronic design automation. Area constraint when routing has become one of the key factors which has great effects on FPGA chips' performances, especially the trade-off between routability and area should be considered carefully. This paper takes the advantages of FPGA's regular routing resources to judge the crucialities of each net to be routed, aims at determining the routing order,which greatly helps to improve the routability based on area-constrained and reduce time cost at the same time. When taking nets' high demand for delay into account, this paper takes full use of mid-length segments.This paper builds an NCJ algorithm routing model, then showes a router consists of NCJ global router and SEGA detailed router which is implemented by C++ program language. Experiment result of that router is compared to that of another router consists of LocusRoute global router and SEGA detailed router, and the algorithm based on NCJ achieves an excellent result in terms of the utilization of routing resouces efficiently.Another issue could not be ingored in designing on high-density devices is crosstalks caused by neighboring parallel segmengts. This paper analyses crosstalks negative effects on circuit performance and showes solutions accordingly.