Transient Analysis Of Power/Ground Network In VLSI

Signal integrity in the power/ground (P/G) bus is emerging as a limiting factor in the nanometer regime VLSI chip designs. Due to excessive IR drops, Ldi/dt noise, electro-migration and resonance effects, P/G grids are more susceptible to current-induced reliability and functional failures. For the design of P/G grids, very scalable transient analysis techniques not only validate the result, but also provide the basis and guide for the optimization process. In this thesis, three algorithms are proposed to deal with the problem. The same basic idea of them is: instead of directly solving the original circuit with different topology, we first do some circuit reductions to transform the original problem to a smaller one in an error-free or error-controlled manner and then solve the reduced network. Our contribution is:An algorithm to compress the RLC chains commonly seen in today's mesh P/G network is proposed. We use circuit equivalent method to reduce all of the intermediate nodes in a chain in an error-free manner. Experiment results show that the algorithm is two orders magnitude faster than standard SPICE and is 10X faster than the most efficient iterative method.Driven by the motivation to further reduce the regular dense mesh-topology grid, we design a multi-grid method based algorithm to reduce the original fine mesh. To construct a series coarse gird on the basis of the fine one, we remove the power line alternately in horizontal and vertical directions. The equivalent circuit technique is use to compress the nodes on the removed line and the float resistor and current source are distributed to the adjacent line by a heuristic rule. Experiment results demonstrate that the method can efficiently deal with the dense mesh-topology P/G grid and has 10X speedup over the existing analogous method when the error is controlled below 1.5%.Finally, we proposed a novel hierarchical approach based on relaxation process, which can deal with general-structured P/G network. Enlightened by the hierarchical method and the ideal of "Divide and Conquer", we first partition the circuit into a series sub-circuit by a partition scheme, then use a relaxation process to stamp the variables of the sub-circuit to the parent circuit, which consists of the boundary nodes. Different from the existing hierarchical algorithm, the relaxation scheme we adopt not only avoids the dense matrix induced by the sub-circuit compression, but also can greatly compensate the error introduced by the circuit partition. We further propose a self-adaptive partition scheme for partitioning the center-bumped P/G grid of high performance IC. Experimental results demonstrate that the new algorithm is more accurate than the existing hierarchical method, reducing to error from 2% to below 0.3% while delivers more speedup over the flat simulators.