Design Of A CMOS Voltage Monitor Chip

With the increasing requirement of electronic products in the modern science and technology field, more and more challenges such as anti-jamming and stability in the microprocessor are brought to electronic engineers. Supervisory technology is one effective way to settle these problems. Voltage monitoring, supervisory integrated circuits are very popular in the designs, in that they cannot only reduce the design complexity and the number of components, but improve system reliability and accuracy significantly, compared to separate ICs and discrete components. Modern supervisory ICs have the characteristic of multifunction, which allows many functions besides voltage monitoring such as watch dog timing, data protection and battery switching. For all these advantages, supervisory ICs have been applied in many fields, including computers, critical μP power monitoring and intelligent instruments.In this thesis, a multifunctional, low-cost, low-consume μP supervisory circuits chip was designed. In this design, the band gap, voltage difference, oscillator and watch dog timer modules were integrated and many functions including power-on reset, watch dog timing, manual-reset and power-down protection were realized. To reduce the consume and cost, the CMOS process was adopted. During the design, we followed full-custom design methodology: confirm the spec-circuit design-simulation-layout design- tap out. The EDA tools used in the design includes the Cadence Virtuoso custom design platform, the simulation tool-Spectre and the verification tool-DIVA.The design was based on the Beiling of shanghai 1.2μmCMOS C12DDR process. The simulation results obtained show that the functions and performances of this supervisory circuits chip meet the spec well.