Research And Implementation Of Buffer Management Algorithms In ATM Switch Supporting Quality Of Service

Asynchronous Transfer Mode (ATM) is defined by ITU-T as switch technology of B-ISDN. ATM can support a variety of traffic (audio, image, data etc.) effectively because of fast packet switching and statistic multiplexing. ATM networks are proved to be advantageous over other forms of communication networks in providing Quality of Service (QoS) guarantee for a variety of traffic types. Buffer management, cell discarding and cell scheduling play key roles in the dynamic QoS control, they continuously receive much attention and investigation. Being in the interest of efficiency and simpleness, buffer management mechanism and cell discarding policy which are justice, easy to carry out and support several type of traffic in ATM switch are studied in depth. This thesis consists of the following:1. Researches on buffer management and cell discarding in ATM switch. By analyzing discrete queuing model, the thesis has a research about the performance of input buffer management, output buffer management and share buffer management. Cell loss probability, throughout, cell delay and buffer utilization are presented by theoretic analysis.2. Studies shared buffer management schemes. Simulations of several buffer management schemes are done under uniform and non-uniform traffic using computer. The thesis analyzes these shared buffer management schemes in cell discarding probability, cell delay, justness etc.3. Proposes an improved shared buffer management scheme. Based on partial shared and pushout schemes, the thesis proposes an improved shared buffer management. By simulating under uniform and non-uniform traffic, the thesis analyzes the scheme's performance and compares with partial shared and pushout schemes.4. Simulates the improved shared buffer management scheme in MAX+PLUS II using VHDL language.