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The Design And Test Of Module In RPR Node

Posted on:2005-02-15Degree:MasterType:Thesis
Country:ChinaCandidate:J Y SunFull Text:PDF
GTID:2168360125958595Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Although products based on Sonet/SDH hold the maximum share in MAN market, they are only designed for the transmission of voice and don't meet the needs of data networks. RPR that adopts the excellence of SDH, ATM and Gigabit Ethernet respectivelyis a better solution to solve this problem.This text is done for designing RPR devices and attains some achievements afterdoing a lot of work as follows:First, from the beginning of analyzing the shortcomings of the transmission data traffic using the tradition SDH, I educe the RPR that can overcome these shortcomings and transmit data, voice and video concurrently, analyze the configuration of its network, MAC and some key techniques in short.Second, after consulting many domestic and overseas journals, proceedings and monograph related to this field and master the principle and mechanism of RPR, I specify the reference model, function model, and describe the key techniques such as resilience, protection switch, fairness algorithm, spatial reuse, topology discovery, broadcast and multicast concretely.Third, basing on grasping the macroscopical model, I analyze the inner configuration and narrate how the RPR node process data efficiently using different priority buffer, the condition of operation of receiving and transferring data traffic, how to prevent the packet from transmitting continuously in the ring , how to solve problems when ring occurs failure and explain the protection protocol rules.Fourth, based on the newest research action and knowing much of the principle of RPR, I set down a feasible designing project and according to its function dividing the RPR into some tiny sections such as receiving module, buffer module, traffic rates policing module, sending module, Mac control sub-layer module and bandwidth control module these six module, describe the principle of receive module, buffer module and send module respectively, design and test this three modules in Verilog HDL.
Keywords/Search Tags:MAN, RPR, Spatial reuse, Verilog HDL
PDF Full Text Request
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