Digtal Frequency Meter Design Based On Cpld And Programming In VHDL

In the electronic design fields, along with the development of computer technique , large scale integrate circuit technique and EDA technique and the abroad application of programmable logic device .traditional design methodology of digital circuit adopting bottom-up , tools , devices has already dropped behind the development of the popular technique. Design technique adopting top-down are taking on more tasks of digital system design . The digital frequency meter design in this paper which adopts top-down design methodology uses the AT89C51 single chip computer as the main controlling parts . The AT89C51 realizes test signal control , keyboard scan and output display of LED. A CPLD chip EPM7128SLC84₁5 fulfills timing logic control and count function .Under the flat of MAX+PLUS II , CPLD software designing , compiling, debugging , simulation and download are been carried out in VHDL language . When opening the strobe, magnified signal and the 50MHz standard signal supplied by system are sent to the two input pins of counters in CPLD at the same time under the controlling of AT89C51.Whenclosing the strobe, two sets of 32 bits counters in CPLD stop counting . Single chip computer reads the counting data in four times to process , then sends the result to display .Via selecting 8 buttons , the system can measure pulse width and occupy-empty ratio of high-level to low-level ,and also including measure frequency of input signals .All the controlling program can be downloaded to 4K byte flash memory in single chip computer .The system combines the controlling flexibility of AT89C51 with programmable performance of CPLD , so it not only can shorten develop cycle , but also has advantage of tightening architecture ,little volume , high reliability , wide scope and high precision .This paper describes the top-down design method , hardware circuit buildup in detail and gives program for CPLD and single chip computer.