Study On The Application Of DSP To Active Power Filter

With the upgrade of the micro-controller, microprocessor and digital signal processor (DSP), the examine and control system of Active Power Filter (APF), which has been developed since 1980's and is a better equipment for harmonic elimination, inclines to digital. In this thesis, the form of DSP+FPGA is applied to APF's examine and control system. Through debugged, it realizes the harmonic examine method based on adaptive linear nerve net. Meanwhile a variable step size (VSS) LMS algorithm is introduced to replace the constant step size case. The theoretical and experiment results shows that the digital examine and control system which adopts VSS LMS algorithm can allow the APF to track changes in the system as well as produce a small steady state error, therefore ensures the speed and precision of APF. Also erase/program FLASH on system and bootload are achieved.