Ti-Al Barrier Layer For Integrating Ferroelectric Capacitor On Si With Copper

Ti-Al film(40 nm),ultra-thin Ti-Al film(4 nm) have been deposited on the Si(001) substrates by magnetron sputtering method. X-ray diffraction (XRD), atomic force microscopy (AFM), four-point probe measurement (FFP), high resolution transmission electron microscopy (HRTEM) have been employed to characterize the barrier performance. Impacts of annealing temperature on the barrier performance of Ti-Al film have been studied. No dramatic increases of surface roughness and sheet resistance have been observed, moreover, no impurity peaks, such as Cu-Si are found in the XRD curves of Cu/Ti-Al/Si heterostructures annealed at temperatures lower than 750℃.HRTEM results indicate that the interfaces of the samples, annealed at 600℃,are sharp and clean, and no obvious reaction or interdiffusion is observed, implying Ti-Al film(40 nm) and ultra-thin Ti-Al film(4 nm) have very good barrier performance up to 750℃.The ultra-thin bilayer Ta(5 nm)/Ti-Al(5 nm) have been deposited by magnetron sputtering, XRD,AFM, FFP techniques have been used to study the barrier performance. No copper silicide is found after 800℃annealing, moreover, Ti-Al film is still amorphous. Surface roughness and sheet resistance of the samples do not increase obviously, demonstrating that the bilayer Ta(5 nm)/Ti-Al(5 nm) can be used as a diffusion barrier layer at annealing temperature of 800℃.Pt/(La0.5Sr0.5)CoO3(LSCO)/Pb(Zr,Ti)O3(PZT)/LSCO/Ti-Al/Cu/Ti-Al/Si heterostructure has been fabricated via both Sol-Gel and magnetron sputtering methods using Ti-Al film as diffusion barrier layers. Ferroelectric tester (Precision LC Unit) has been used to measure the ferroelectric properties.It is found that the LSCO/PZT/LSCO capacitor has very good saturated ferroelectric loop, remnant polarization and coercive voltage of LSCO/PZT/LSCO capacitor, measured at 10 V, are～18.0μC/cm2 and～0.7 V, respectively. Ti-Al film is used as diffusion barrier layer between Cu and Si as well as oxygen barrier layer between Cu and oxide electrode, providing very important data for integrating Si based ferroelectric random access memory with Cu metallization.