| High efficiency synchronous step-down DC/DC converter have been analyzed and designed in details in this thesis. Based on the sync-rectifying technology,PWM/PFM operation-mode and peak-current mode were also used. First, step-down DC/DC converter was analyzed and the whole block diagram according to the features was designed in this thesis.Then,each functional cells were analyzed and designed, which included folded-cascode error amplifier, low-dropout voltage regulator, band-gap voltage and current references,oscillator with high frequency and narrow width pulse and synchronizable to an external clock signal,current sence and convert circuit, PWM/PFM comparator,dead-time control circuit, electrical level shift circuit,slope compensation circuit, several protection circuits and power MOS et al.These functional blocks have been selected and designed in transistor level according to the chip parameters,they have been simulated by chrt 0.35μmCMOS model of Cadence,the results all satisfy the require of chip design.Next, process flow and layout are introduced , meanwhile the plane and route, components matching, para-effect are considered.Finally,the chip layout has been accomplished according to the design rule.
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