Research On Time-relay Intelligent Measuring Instrument

In the electronic field, along with the development of the computer technique, large scale integrate circuit technique and EDA (Electronics Design Automation) technique and aboard application of programmable logic device, traditional design methodology of digital circuit adopting bottom_up, tolls, devices has already dropped behind the development of the popular technique. Design technique adopting top_down are taking on more tasks of digital system design. The smart time relay meter design in this paper which adopts top_down design methodology uses the AT89S52 single chip computer as the main controlling parts. The AT89S52 single chip computer realizes test signal control, keyboard scan and output display of LCD. A FPGA (Field Programmable Gate Array) chip (ACEX 1K30) fulfills measuring time relay/measuring frequency, dividing frequency of time reference, timing logic control, count and output function. Under the flat of Quartus II, FPGA software designing, compiling, debugging, simulation and down are been carried out in VHDL(Very High Speed Integrated Circuit Hardware Description Language) language. A start signal is given under the controlling of AT89S52. when the choice of measuring time relay, strobe signal opens under the controlling of the time relay signal, the time relay signal and the bade time signals were sent to base counter input counting began at the same time, when the gates closed at the counter signals are synchronized to stop counting, the single chip computer would read 12 metric counting data to his memory in FPGA then process the counting data, and the last sent the results of the counting data to LCD display. Through the local keyboard or remote operation panel can be programmed, respectively measuring time relay / measuring frequency control, but also to counter the open, and stop counting functions of control, the various counters can also be initialized. In addition the system not only can test time of the time relay, but also can test the signal frequency. The single chip computer of AT89S52 includes 256 bytes of RAM and 8 K bytes of flash memory, so all controlling program can be downloads to the single chip computer. The system combines the controlling flexibility of single chip computer with programmable performance of FPGA chip (ACEX 1K30), so it can not only greatly shorten developed cycle, reducing the design costs, but also enable the system is compact, small size, weight light, high reliability measurement of time / frequency range wide, high precision advantages. It fills the blank of a certain type time relay of test for the smart instrument in my air force. It has a high economic and military value. This paper discusses in detail the different parts of the system hardware circuit, single chip computer, FPGA design, software programming and top-down design methods and so on.