Underwater Communication Beacon Signal Born And Digital Filter Based On FPGA

The thesis is in order to study underwater communication technique which is based on FPGA, and has solved two important problem, one is underwater communication beacon signal born , the other is digital filter. The beacon signal is the reunite signal of linear FM signal and pulse code signal, and the pulse code signal is used as a token of emit signal.By using VHDL, the thesis introduces the method of generating 255 bit pulse code signal with 8 level feedback shift register generator, and the method of generating beacon signal by searching table, and the method of generating 128 level FIR digital filter by searching table segment by segment and distribution algorithm. Among these methods, some are technical, such as generating memory initialization file, reference m series and encoded m series plus beforehand, the use of linear phase cause and effect FIR filter coefficient even symmetry feature, the realization of multiplication and addition by using distribution algorithm, searching table segment by segment, add shifting.The VHDL programs which are offered in this thesis are all passed the simulation on Altera's Cyclone series device.By using VHDL, it is convenient to realize the design of DSP control chip on FPGA device, such as, counter, status machine, logic control. For DSP algorithm chip, by using the EAB in the FPGA device and the table searching method, it is possible to realize the design of the algorithm chip, which the computation is simple and the capacity is little.In addition, there are some advantage for the design of the device which the structure is same and the behavior is different by using VHDL.