Study On Data Acquisition System Of Coal Mining Water Inrush Monitoring Based On FPGA

The coal mining water inrush is one of the five coal mine disasters, which invariably perplex and limit the coal production. With the majority of our coal seam mining into the Deep place, mining depth, mining strength, mining speed, mining scale of the increase and expansion, water inrush disaster has shown a trend of high, in recent years. For the imperfect situations, that the water inrush monitoring parameters is single and the deficiency of dynamic monitoring, this paper studies a novel water inrush multi-parameter monitoring data acquisition system based on FPGA (Field Programmable Gate Array) technology.Firstly, this paper discusses the technical features and basic structure of FPGA. Altera's Cyclone EP1C6Q240C8 chip Selected as the system core of the data processing and control. Then, introduces the typical FPGA development process, Verilog hardware programming language (Verilog HDL), Quartusâ…¡integrated design platform and Modelsim simulation tool. In addition, because of the underground environment is poor and water monitoring points are random, the system uses the CAN bus technology to communication with PC. In the section of the basic theory, through the analysis of coal mine water inrush disaster warning theory, four physical quantities extracted as monitoring objects, which before coal mine water inrush are obviously changed. They are temperature, stress, strain and pressure .Then, briefly describes the data collection techniques and Coal mine monitoring system design principles.In this paper's system hardware design section, the key factors of the design and the implementation process have done a detailed description, includes:power, clock, AD conversion, CAN bus interface and download circuits. Focused on the power circuit and AD conversion circuit:Isolate power supply mode used in the power circuit to reduce interference, respectively to input / output interface circuit and system internal circuitry; AD conversion using the AD7862 chip four-channel analog input, two signals at the same time sampling, the maximum single channel Sampling frequency of 125KHz. Subsequently, briefly introduced the measures of anti-EMI, in this design.In the software design section, this paper introduces FPGA inside various sub-modules'specific features and design methods. The designs of clock module and digital filter, FIFO buffer are designed and implemented using Mega Wizard Plug-In Manager, in the Quartusâ…¡. AD conversion control module and CAN bus Interface module are designed using FSM (Finite State Machine). Software programming using Verilog HDL, system software ensures maximum portability. And the system function tested to verify the implementation of design functions.Finally, based on the results the paper summarizes the data acquisition system research, and future research directions are suggested.