Acquisition Algorithm Research And FPGA Implementation Of GNSS Receiver

Global navigation satellite system (GNSS) is widely used in the area of positioning and navigation, geodesy, marine vessels and vehicles monitoring and other fields. GNSS has the advantages of the GPS, GLONASS and China Compass satellite system, through combinatorial navigation and position it can provide users with more accurate information about position, velocity and timing. However, the satellite signal will be seriously impaired in complex environments such as interior, forests and urban ones. It will get worse in high-dynamic situation. As a result, a traditional GNSS receiver can hardly capture and track the navigation satellite signals, which puts great limits to the GNSS applications. Nowadays, researchers have devoted themselves to high-sensitivity receiver technology. With advanced algorithms, it is possible to capture and track the weak GNSS signal, and realize position navigation under high-dynamic enviroment.Fast aquisition is one of the critical technologies that guarantees the GNSS receiver's real-time and high-precision characteristic. This thesis focuses on the acquisition algorithms research, and puts forward three approches, including serially searching, FFT-based parallelly searching in time-domain and "Multi-Match filter & FFT"-based parallelly searching in both time-domain and frequency-domain. The third algorithm can search the code phase and Doppler frequency at one time, which make it suitable for fast acquisition in high-dynamic environment. To improve the detection probability of weak signals, the traditional non-coherent accumulation algorithm is replaced by differential coherent accumulation. Theoretical analysis and simulation were implemented to demonstrate the superiority of the differential algorithm.On the other hand, the FPGA designs of acquisition algorithm has been detailed in this thesis. The conventional matched filter is designed based on delay line, results in a great consumption of FPGA resources. Therefore, folded-filter and PPT structure based filter algorithms are put forward. Both of the two algorithms can significantly reduced hardware resource occupied.