Research On Power Amplifier And High-Precision Modeling Of On-Chip Devices For Millimeter-Wave Communications

In recent years,with the rapid development of mobile communication services,users’demands for communication transmission rates are increasing day by day,and there is an urgent need to improve the bandwidth and spectrum utilization of wireless communication systems.At present,the Sub-6GHz frequency band is quite crowded,and the millimeter-wave frequency band plays an increasingly important role in the development of mobile communications due to its large available bandwidth and abundant spectrum resources.In order to improve spectrum utilization,wireless communication systems usually use high-order modulation technology,which lay stress on the linearity of transmitter front-end,and the nonlinear distortion of the transmitter front-end is mainly due to the power amplifier.Therefore,millimeter-wave high linearity power amplifier has become a research hotspot.High-precision device equivalent circuit model is one of the key techniques of millimeter-wave integrated circuits,and the lumped equivalent circuit model of on-chip device provides the foundation for integrated circuit chip design.High-precision equivalent circuit models is helpful in improving simulation accuracy and reducing integrated circuit design iterations.The millimeter-wave high-linearity power amplifier and high-precision on-chip device equivalent circuit model are important in millimeter-wave integrated circuit design.For the fifth-generation mobile communication（5G）base station wireless backhaul application in E-band,an E-band high linearity power amplifier is designed in this paper and implemented in40nm CMOS process.The test results of the power amplifier show that,at 81GHz,the output power at the 1d B compression point(P_{1d B})and saturation output power(P_sat)of the power amplifier are11.2d Bm and 12.7d Bm,respectively,and the power-added efficiency at the 1d B compression point(PAE_{1d B})and the maximum power-added efficiency(PAE_max)are 15.6%and 17.5%,respectively,and the power-added efficiency(PAE@(P_sat-6d B))at 6d B power back-off（PBO）is 6.5%.To further improve the output power of the power amplifier,an E-band power amplifier using power combining technique is designed and implemented in 40nm CMOS process.The test results of the tape-out chip show that,at 81GHz,the P_{1d B} and P_sat of the power amplifier are 13.8d Bm and15.4d Bm,respectively,the PAE_{1d B} and PAE_max are 13.6%and 18.2%,respectively,and the PAE@(P_sat-6d B)is 5.9%.Traditional modeling process of field effect transistor leads to potential non-physical and non-optimal multiple solutions.This paper presents a novel methodplogy for parameter extraction,verification and circuit calibration for lumped element small-signal equivalent circuit model of FET,using characteristic-function-based analytical iterations.The present method can verify and screen non-physical multiple solutions pertaining to conventional approaches,and also serve as an effective tool for circuit calibration.Relevant work has been published in the journal of Solid-State Electronics.A de-embedding technique for on-chip interconnects and resistors based on Thru structure is presented in this paper,and relevant work has been published in the journal of Microwave and Optical Technology Letters.