Signal Integrity Modeling And Analysis For Memristor Crossbar Array In Neuromorphic Chips

Artificial intelligence has been widely used in medical services,finance,security,education,transportation and logistics industries,and the only physical support for its further development is the neuromorphic chip.With the development of neuromorphic chips in the direction of miniaturization,high integration and high speed,the signal integrity problems will become an important factor limiting the industrial design and mass production of neuromorphic chips.The neuromorphic chip adopts new signals,new devices,new architecture,and new computing modes compared with traditional chips,so the signal integrity problems for such chips are more challenging than traditional chips,and their signal integrity modeling and analysis methods still have theoretical deficiencies and technical bottlenecks.This thesis will conduct research on a very representative branch of neuromorphic chips based on memristor arrays.At present,there are three main problems that need to be broken through: first,the modeling and analysis of equivalent circuits of neuromorphic memristor arrays,that is,how to quickly and accurately model and analyze parasitic parameters of memristors,interconnects and other structures;Second,the modeling and analysis of the spiking signal sequence of the neuromorphic memristor array,that is,how to map the ideal spiking signals in the spiking neural network algorithm to the actual waveform suitable for the memristor array;Third,the algorithm optimization design of the neuromorphic memristor array,that is,how to optimize the algorithm to improve the performance of the neuromorphic memristor array.In view of the above challenges,this paper carries out the modeling and analysis of the signal integrity of neuromorphic chip based on memristor array in three aspects: equivalent circuit modeling,spiking signal modeling and algorithm optimization,and the main research contents are as follows:1.Aiming at the problem of equivalent circuit modeling and analysis of neuromorphic memristor array,this thesis develops a memristor array equivalent circuit modeling method based on Partial Element Equivalent Circuit and Domain Decomposition Method.The proposed circuit modeling method includes the improved compact model of memristor and interconnect parasitic parameters,and is suitable for crossbar arrays of any size.It can achieve fast conductance value update of memristors as well as simulation of neural network training and testing process in the time domain.Based on this model,the parasitic effects on the performance of artificial neural networks based on memristor array is studied.2.Aiming at the problem of modeling and analysis of spiking signal sequences for neuromorphic memristor array,this paper proposes a spiking signal sequence encoding method,which can realize spiking neural network training based on Spike Timing Dependent Plasticity(STDP)together with memristor arrays.In this thesis,the influence of spike firing rate and waveform parameters on the input encoding accuracy in the proposed encoding method is analyzed,in which the spike firing rate is the main influencing factor,and the influence caused by the change of waveform parameters is very limited.Combined with the memristor array equivalent circuit model,the influence of parasitic effects on spiking signal waveform,STDP rule implementation and spiking neural network training accuracy is analyzed,which proves that the proposed encoding method has the advantages of low power consumption and good anti-interference ability for parasitic effects.3.Aiming at the problem of algorithm optimization design of neuromorphic memristor array,this thesis proposes an improved unsupervised STDP rule,which can achieve more comprehensive weight adjustment in the training process of spiking neural network compared with the traditional STDP rule,and has more advantages in both algorithm and memristor array implementations: at the algorithm level,the improved STDP rule and the traditional STDP rule achieve 85.90% and 82.81% recognition accuracy for MNIST handwritten digits,respectively,which proves that the improved STDP rule can achieve a higher recognition accuracy;At the hardware level,a memristor array circuit training simulation method suitable for the improved STDP rules is proposed,and the average power consumption of the improved STDP training process is 21.5% lower than that of traditional STDP,and the robustness of the two cases on the non-ideal characteristics of the circuit and memristor is similar.