Research On Missile-borne SAR Imaging SoC Design

Synthetic aperture radar（SAR）is an all-weather microwave remote sensing technology,while missile-borne SAR is an important application of SAR imaging system.Because of the partic-ularity of its application,missile-borne SAR imaging system usually requires signal processing in a short time.In addition,with the development of the integrated circuit manufacturing tech-nology,the demands of missile seeker for miniaturisation and low power consumption of the SAR imaging system are becoming higher and higher.However,the SAR imaging algorithm is highly complex,the amount of radar echo data and the amount of computation required for imag-ing are very large,which improves the design complexity of SAR imaging system.Although the existing radar signal processor technology has developed rapidly,for the SAR imaging sys-tem designed with advanced processor,the image processing time is mostly in the second level,which means that the real-time performance is not good enough,and often faces the problems of too large scale and high power consumption.Therefore,the research on the new processor with the characteristics of highly real-time performance,small scale and low power consumption has high academic value and application value.According to the special application requirements of missile-borne SAR imaging system,a reconfigurable missile-borne SAR imaging SoC de-sign is proposed in this paper.The main research results and innovation points are as follows.（1）In order to solve the problems of poor real-time calculation,too large scale and power con-sumption of SAR imaging system based on advanced processor,the architecture of missile-borne SAR imaging SoC is designed,which improves the real-time performance of the SAR imaging system and reduces the scale and power consumption.In this paper,the configurable SAR imaging SoC architecture is designed by dividing the computing nodes of SAR imag-ing algorithm,and the algorithm is realized by IP core integration,which mainly includes four IP cores:fast Fourier transform（FFT）,Doppler parameter estimation,corner turning memory（CTM）and arithmetic acceleration unit（ACU）.The static reconstruction of hardware is com-pleted by using CPU and parameter analysis circuit to load parameters.At the same time,the hardware system for IP core development and SoC verification is designed and fabricated,and the missile-borne SAR imaging SoC is realized by using the standard integrated circuit design flow.（2）In order to solve the problem of single function and poor reusability of traditional FFT oper-ation circuit,this paper presents a configurable FFT IP core design method,which extends the calculation function of the designed FFT IP core.In order to meet the operation requirements of different SAR imaging algorithms,the proposed FFT IP core has the functions of variable points(i.e.2³～2¹³point FFT transform),positive and inverse variable（i.e.Both FFT and IFFT）,variable extraction mode（i.e.Both time-based decimation and frequency-based decimation）and variable working mode（i.e.Both discrete processing and continuously processing）.Mean-while,in order to improve the real-time performance of the proposed SAR imaging SoC,the FFT algorithm is carefully studied,and the FFT IP core and its internal sub-modules design are completed.The simulation results show that when the working frequency is 100MHz,the FFT IP core designed in this paper can complete the 8192-point floating-point data transformation with 82.7μs,and the performance is better than that of the common FFT operation processor in the SAR imaging system under the same conditions.（3）In order to solve the problem that the hardware overhead of Doppler parameter estimation based on signal processing is too large,an optimal design method of balancing parameter esti-mation accuracy and hardware overhead is proposed in this paper,and the IP core design and logic resource optimization of Doppler parameter estimation are realized.Taking several com-mon Doppler parameter estimation algorithms in SAR imaging system as examples,this paper uses MATLAB tool to complete Doppler parameter optimization evaluation.Finally,it is ver-ified by FPGA board level system that the purpose of logic resource optimization and Doppler parameter estimation error control is achieved.（4）In order to solve the problem of low matrix transposition efficiency faced by traditional CTM design technology,an efficient CTM IP core design method is proposed in this paper to improve the matrix transposition efficiency.The designed CTM IP core improves the matrix transposition efficiency of SAR imaging system to more than 99%,which is much higher than that of the traditional CTM design method.In this paper,according to the characteristics of SAR imaging application,the SDRAM memory access strategy is optimized,and the matrix data interleaving pattern is designed to overcome the bottleneck of the system data flow,so that the data processing bandwidth in the chip is close to the full width,thus ensuring the real-time implementation of the SAR imaging algorithm.（5）Aiming at the changeable phase compensation operation in SAR imaging algorithm,this paper proposes a calculation model of phase compensation function,which reduces the diffi-culty of phase compensation operation in SAR imaging algorithm.In this paper,by designing the ACU IP core of unified architecture and using the calculation method of”CPU and ACU”,various complex operations can be realized simply and flexibly,and the design complexity of SAR imaging SoC on reconfigurable missile can be reduced.Finally,in order to reduce the hardware overhead,the core CORDIC circuit module in ACU IP core is designed by using one-step cyclic iterative structure.Based on the above research work and the research results,the chip characteristics,the real-time performance and the imaging resolution of the designed missile-borne SAR imaging SoC are analyzed,and the design idea and concept of the full text are verified.The designed missile-borne SAR imaging SoC chip is realized by 0.13μm standard CMOS process.The chip area is 13mm×13mm,the working frequency is 100MHz,and the power consumption is 4.98W.When the original radar echo size is 8192×2048,the imaging processing time based on forward range Doppler（RD）imaging algorithm is 471.5ms,and the imaging processing time based on forward squint RD imaging algorithm is 387.2ms.Therefore,the designed SoC reduces the processing time of single frame image to millisecond level,and has the characteristics of highly real-time performance,small scale and low power consumption.