The Research On Scability Of Van Der Waals Integrated Two-Dimensional Semiconductor Devices And Its Application

The development of the semiconductor industry has encouraged human society to enter the information age and shift towards the intelligent age.However,because of the size of silicon-based transistors has come close to the physical limit,the semiconductor industry is facing new and enormous challenges and opportunities.The family of two-dimensional（2D）materials is rich and covers almost the whole range of material properties.In addition,the thickness of monolayer 2D materials with an atomically smooth surface is less than 1 nm.Thus,2D materials have great potential for“More Moore”and“Beyond complementary metal-oxide-semiconductor（CMOS）”technologies,and are expected to be a promising type of material in the post-Moore era.As a representative of a class of 2D material,transition metal chalcogenide（TMDs）contains abundant physical properties.At present,there are many advancements not only in the large-scale manufacturing of 2D TMDs,but also in the app lications of 2D semiconductor transistors and digital circuits.International Roadmap for Devices and Systems（IRDS）have planned to introduce 2D materials into the semiconductor industry around 2028,which is of great significance to promote the practical application of 2D semiconductor devices and the development of semiconductor industry.In order to improve the electrical contact of 2D transistors and solve many challenges in the application of 2D semiconductor electronics,we have done some research works on the scalibility and applications of van der Waals（vd W）integrated2D semiconductor electronics.The main contents are as follows:（1）Two-dimensional vd W contact was fabricated by CVD method.The controllable synthesis of 2D vd W metal/semiconductor heterostructure arrays is an effective way for the integration and application of 2D materials,which can be directly applied to fabricate vd W contact.However,usually the growth of vd W heterostructures suffers random nucleation and is hard to manufact vd W heterostructure arrays.How to control nucleation and achieve robust synthesis of vd W 2D heterostructure arrays is a big challenge.To this end,we create defect arrays on 2D semiconducting TMDs（s-TMDs）by laser etching for the selective nucleation and growth of metallic TMDs（m-TMDs）.Therefore,we achieve robust synthesis of a series of vd W m-TMDs/s-TMDs heterostructure arrays including VSe₂/WSe₂,VSe₂/WS₂,VSe₂/MoS₂,Ni Te₂/WSe₂,Co Te₂/WSe₂ and Nb Te₂/WSe₂.Through the characterization of atomic resolution cross-sectional transmission electron microscopy（TEM）,it is demonstrated that the interface of as-prepared m-TMDs/s-TMDs heterostructures is atomically clean and damage-free.Based on the VSe₂/WSe₂ heterostructures,the high-performance bilayer WSe₂ transistor with vd W contact is fabricated,and the current density is up to 900μA/μm,showing the great potential of the electrical properties of 2D transistors with vd W contact.（2）The scalability of vd W integration technology.Conventional vd W integration technology is usually limited to small-scale integration with high alignment accuracy,and cannot achieve large-scale vd W integration with high-precision alignment.How to achieve large-scale and high-precision alignment of vd W integration technology is an important challenge.Hence,we reported a wafer-scale vd W integration strategy with high-precision alignment.The pick-up and release of large-area PMMA/electrodes layer can be effectively controlled by carefully optimizing the interfacial force between PDMS stamp and PMMA.Meanwhile,conventional mark alignment of ultraviolet lithography is used to achieve large-area and high-precision alignment of scalable vd W integration technology and then the alignment errors are only a few microns envn in wafer-scale vd W integration.Moreover,our large-area vd W integration strategy try to use mature manufacturing technology in semiconductor industry as much as possible.Therefore,the scalability of vd W integration is realized from three aspects including high industrial compatibility,wafer-scale and high-precision inter-layer alignment.As a consequence,the scalability of vd W integration will promote the integration of 2D semiconductor materials and semiconductor industry,and accelerate the application of2D semiconductor electronics.（3）Improving the performance uniformity of 2D transisitors using large-scale vd W integration.The performance uniformity of 2D transistors over large area is very important for the practical application of 2D transistors in integrated circuits.Currently,the research on the performance uniformity of 2D semiconductor devices mainly focuses on the large-scale manufacting of high-quality 2D materials.Researches about how to improve the uniformity of device performance as much as possible in device fabrication process are limited.The conventional metallization process may introduce random defects or surface contaminations of atomic 2D semiconductors resulting in device-to-device variation.The fabrication of atomically clean and damage-free vd W contact over large-area is considered to be a feasible approach.Herein,we demonstrated that monolayer MoS₂ transistors with vd W contacts have better uniformity and reproducibility than the conventional MoS₂ transistors with deposited metal contacts.By the systematic comparison of different electrical parameters of transistor,it is found that the vd W integrated devices show better performance and more uniform performance distribution.Furthermore,we fabricated a high-performance vd W integrated MoS₂NMOS inverter with the gain up to 585 and the noise tolerance up to 97%at V_dd=5 V.The logical circuits including NOR,NAND,and AND logical gates and half-adder circuits are further fabricated using vd W integration process and all logical circuits have correct logic function.Therefore,vd W integration technology has great application potential in large-scale integrated circuit based on 2D semiconductors,which will effectively promote the“Lab-to-Fab”transition.