Research On Low-Power High-Precision TDC In ETL Timing Detector For The CMS Phase-Ⅱ Upgrade

The Large Hadron Collider(LHC)is the largest and most energetic proton accelerator in the world.It plays an important role in physical research fields such as the origin of particle mass,supersymmetric physics,and dark matter.The Compact Muon Solenoid(CMS)is one of the important general-purpose detectors on the LHC.LHC will be performed Phase-II upgrade for the third Long Shutdown(LS3)from 2025 to mid-2027.After the upgrade,the collision’s centroid energy will reach 14 TeV,the peak luminosity will reach 5×1035cm-2s-1,and the stacking events of each collision cycle will reach 200 PU(Pileup).In order to allow the CMS detector to work under the conditions of 2.5 times the current luminosity and 5 times the current stacking event during LHC Run4～5(2027-2038),a MIP(Minimum Ionizing Particles)timing detector needs to be installed during the upgrade and can be used to accurately measure the arrival time of the particles,thereby improving the particle reconstruction performance of the detector.The ETL(Endcap Timing Layer)of the MIP timing detector uses the LGAD(Low-Gain Avalanche Detector)sensor and the ETROC(ETL Readout Chip)readout chip scheme.The TDC(Time-to-Digital Converter)in ETROC needs to have higher time resolution,wider dynamic range,and lower power consumption.The main research work of this dissertation is to develop a TDC with a gated circular delay chain structure against the background of the time measurement of the ETL timing detector in the Phase-II upgrade of the CMS detector,aiming to solve the complex problems and severe challenges faced by electronics design about the readout of the time information measurement in the ETL timing detector.The detailed research content and innovation points are shown in the following:1.A new architecture TDC with gated circular delay chain and resistible radiation feature is proposed:the 63 customized layout two-input NAND gates are connected end to end to form a gated circular delay chain,and the measured pulse controls the oscillation of the circular delay chain,thereby reducing the power consumption of the circuit.Using the ELT(Enclosed Layout Transistors)layout NAND gate significantly enhance the circuit’s anti-radiation ability.The circular delay chain can simultaneously measure the Time of Arrival(TOA)and the Time over Threshold(TOT)of the pulse,which improves the measurement efficiency.The test results of the ETROC 1 TDC chip designed with this structure under 1.2 V power supply and room temperature conditions show that the average Bin Size of the delay chain is 17.8 ps.When the event hit occupy is 1%,the power consumption of the TDC is only 97 μW.The X-ray irradiation experiment results have demonstrated that the TDC with this structure still works normally after being irradiated with a total dose of 23.8 KGy.2.The problem of delay cell calibration in the delay chain is solved.The 320 MHz clock adjustable pulse calibration scheme can accurately obtain the average delay time of the delay unit:two pulses of the 320 MHz clock are selected as the measured signal of the TDC,each time TDC measurement will generate a set of calibration data,and its statistical analysis can achieve the average delay time of the delay unit.The test results of the ETROC1 TDC chip show that the accuracy of the average delay time obtained by this calibration scheme is 99%.The accuracy of the average delay time obtained by the further correction has been increased to 99.9%.3.A TOA test method for clock catching up is proposed,which can measure the TOA time-to-digital conversion performance more efficiently and accurately:using 40.001 MHz clock as the measurement pulse of the TDC,it catches up with the TDC system clock(40 MHz).The TOA time measurement transfer curve can quickly obtain.The test results show that the time resolution of TOA is 17.8 ps,the measurement dynamic range is 11.6 ns,the integral nonlinearity is less than ±1 LSB,the differential nonlinearity is less than±0.6 LSB,and the time measurement accuracy is better than 9.9 ps RMS in the full range.4.Proposed an optimized solution for segmentation and decoupling compensation of the TDC power supply,thereby improving the power supply stability of the delay chain circuit and reducing the power supply noise:according to the test results of the ETROC1 TDC chip,the single power supply of the ETROC1 TDC is divided into the analog and digital power supply,the analog power network decoupling capacitance was increased from 60 pF to 443.5 pF.The simulation results show that the optimization scheme reduces the oscillation amplitude of the analog power supply by about 60%.The optimized ETROC2 TDC chip was taped-out in July 2021.The performance test and irradiation test of the ETROC1 TDC chip have been completed in the SMU Optoelectronics Laboratory,and the test results meet the design requirements.The performance of ETROC1 TDC has been further verified in the singlechannel link chip.The verification results show that the jitter of the output pulse arrival time(TOA)of the discriminator is only 8.5 ps,and TOT is used to correct the TOA to obtain a more accurate arrival time.It is expected that the ETROC2 TDC chip will be tested in November 2021.After the test results meet the design requirements,the ETROC2 TDC will be applied to the ETROC2 chip under development.