Study On CMOS Terahertz Detector And Circuit Design

Terahertz wave has attracted more and more attention for their safety,perspective,and information carrying capacity while terahertz detector is the core of Terahertz technology.Compared with other types of terahertz detectors,CMOS terahertz detectors have become a hot spot due to their low cost,low power consumption and high integration.Based on the existing results of the laboratory,this paper propo ses an asymmetric MOSFET terahertz detector structure and studies its performance from principle,simulation and experiment.The amplifier circuit is designed and optimized for the terahertz detection array.The conclusion of the thesis include the following three aspects:1.A novel CMOS terahertz detector based on asymmetric source-drain structure was fabricated using standard 0.18?m process.The simulation results show that reducing the overlap area between gate and source LDD can effectively reduce gate-source parasitic capacitance CGS and improve detector performance.By adding a small Block area to NSD mask in the standard process,the asymmetric structure detector is prepared and its performance is characterized.Experimental results show that the voltage response Rv of the detector is 155%higher than that of the standard symmetric detector structure,and the noise equivalent power is reduced by 70%.2.The frequency characteristics of the prepared terahertz detector are characterized.A double lens terahertz imaging system is built based on the detector and the resolution of the imaging system is characterized.The influence of source nonuniformity on measurement is studied as well.The results show that the detector has high response between 250GHz and 650GHz,and the resolution of the imaging system is about 3 mm.3.Amplifier circuit for detector array is designed and optimized.According to the terahertz detector array structure,the area optimization design of 40dB amplifier on chip is carried out and a large amount of chip area is saved.The first-stage amplifier circuit is arranged in the pixel unit while the second-stage and the third-stage amplifier circuit are shared in rows.The decoder is designed to control the input and output of pixel cells in the array.The simulation results show that the gain,phase margin and equivalent input noise of the optimized amplifier are 40dB?63.72°?6.56nV/Hz0.5@1KHz respectively,which meet the design specifications.