Research On Read And Write Optimization Methods For High-Density Resistive Memory Arrays

Resistive memory can achieve higher memory density,lower nondestructive read latency,and higher energy efficiency than dynamic random-access memory used in conventional memory systems.These advantages make resistive memory become a promising candidate for next-generation nonvolatile memory.Cross-point memory arrays can be used as the basic core building blocks for constructing high-density resistive memory.However,during the basic write and read operations,intrinsic nonidealities of cross-point memory arrays,including IR drop,sneak current,cycle-to-cycle write variation,and cell current–voltage nonlinearity,significantly degrade the write performance as well as write and read reliability.Although multilevel cell and three-dimensional(3D)array integration can further improve the density of cross-point memory,the coupling effects of array nonidealities further aggravate the degradation of performance and reliability during write and read operations.Therefore,overcoming the effects of nonidealities becomes a hot research topic for highdensity resistive memory arrays.In this article,from the perspective of the basic memory array operations,operation optimization methods for high-density resistive memory arrays that matching and mapping the operation type and parameters with the nonideal array characteristics are explored,for the purpose of forming practical energy-efficient storage-class memory systems.To solve the problem of high write latency of 3D cross-point memory arrays caused by coupled IR drop and sneak current,a write latency optimization method that adapts to multidimensional non-uniformity of cell effective write voltage is proposed.The method adapts to the cell-to-cell and state-to-state non-uniformities of cell effective write voltage by exploiting 3D address and two types of data patterns and dynamically determining the actual write latency,which effectively improves the write performance.Characteristics and effects of interlayer half-selected cells and interlayer sneak currents in 3D cross-point memory arrays under 3D 1/2 bias scheme are analyzed.Accessing the two boundary memory layers is found to have lower write latency and lower array power consumption than accessing intermediate memory layers.To make the 3D cross-point memory system adapt to the impact of multidimensional non-uniformity of cell effective write voltage on the actual write latency,dynamic measurement and synthesis of the 3D address,the number of selected low-resistance-state cells,and the number of half-selected low-resistance-state cells are proposed.A multidimensional write latency table is dynamically indexed according to write operation parameters,to accurately set the write latency of resistive cross-point memory and reduce the average write latency.Evaluation results show that compared with the existing approach that sets the write latency according to bit-line data pattern,the proposed crosspoint memory array multidimensional write method can reduce the memory access latency by 64.1% and improve the system performance by 3.4 times on average.To solve the problem of narrowed read margins of multilevel cell cross-point memory arrays caused by IR drop and sneak current,a read margin optimization method that adapts to the non-uniformity of bit-line output currents is proposed.The method effectively improves the array read reliability by optimizing the array read bias scheme and setting the array read references by bit-line groups.To reduce the IR drop for enlarging array read margins,unselected word-line grounding with unselected bit-line partial biasing parallel read scheme is designed.The scheme eliminates the sneak current and IR drop along the selected bit-lines and makes the bit-line output current independent to the location of the selected word-line.For improving the cell effective voltage,the bias scheme regulates the IR drop along the selected word-line by adjusting the partial bias coefficient of unselected bit-lines.Based on the observation that the array-level read margin shrinks with the bit-line read reference sharing granularity increasing,a bit-line location adaptive multilevel read reference setting method is further proposed.The method groups neighboring bit-lines by a specific granularity,and different multilevel read reference values are set for different bit-line groups.Compared with the method that shares multilevel read reference values in the entire cross-point memory array,the proposed method can distinguish all the 16 resistance states in the cross-point arrays with size of 512×512 and can improve the normalized array-level read margin from-1.04 to 0.23.To solve the problem of high write latency and high write-error rate of multilevel cell vertical 3D cross-point memory arrays caused by coupled IR drop,sneak current and cycleto-cycle write variation,a write operation multidimensional optimization method which overcomes cell voltage non-uniformity is proposed.The method improves the write performance and reliability by optimizing array write bias scheme and thus reducing the coupling effects between array and cell nonidealities.The proposed dual-transistor array structure uses a two-transistor-n-resistor cell organization to reduce the current driving requirement and the voltage drop across each vertical-pillar access transistor.Multiside asymmetric bias improves the resistance-switching speed of the selected cells by exploiting the current-dividing effect along the selected vertical pillars.Proportional-control multilevel state regulation reduces the average number of write-and-verify iterations by leveraging the dependence of cycle-to-cycle write variation on the write pulse amplitude.Multilevel cell parallel writing strategy improves the in-array cell-level write parallelism by utilizing the passing-through characteristic of intermediate resistance states.Thus,the write performance is improved from three dimensions.Also,variation-aware logarithmic-scale multilevel cell state division reduces the worst-case write-error rate by utilizing the dependence of variation on the target resistance state.Compared with the existing methodology based on singletransistor array structure with multidirectional write driver,the proposed comprehensive optimization method for array write operations that overcomes cell voltage non-uniformity can reduce the average access latency by 27.5% and the energy consumption by 37.2%.