Algorithm And Architecture Of MIMO Preprocessor For Future Wireless Communication

In modern society,wireless communication has been an indispensable part of our life,which opens our eyesight to the whole world.With the rapid development of the society,however,wireless communication is confronted with difficult challenges.On the one hand,the newly-developing scenarios,such as the virtual reality(VR),the Inter-net of Things(Io T),intelligent manufacturing,are putting forward higher requirements for wireless communication,in terms of the Throughput,latency,reliability,etc.On the other hand,the available spectrum resource for wireless communication is very limited.Therefore,to enhance the spectrum efficiency is imperative for wireless communication.MIMO technique has attracted considerable attention for its dramatic improvement on spectrum efficiency without notable increment in power consumption.Scaling up the MIMO systems is a potential way of solving the contradiction between the high data re-quirement and limited spectrum resource.However,several obstacles still exist before the practical application of larger-scale MIMO technique,of which the data detection is among the most crucial issues.MIMO detection entails complicated matrix calculation,such as sorted QR decompo-sition(SQRD),lattice reduction(LR),matrix inversion,etc.With the number of antennas grows,traditional MIMO detection algorithms suffer from severe performance degrada-tion in terms of the complexity,throughput,and latency.Therefore,it's imperative to develop new MIMO detection algorithms for future wireless communication.Based on this background,the contribution in this paper can be summarized as follows.SQRD is extensively adopted in MIMO systems,and the existing works about SQRD mainly focus on the decomposition process because the sorting process is inconspicuous in smaller scale MIMO systems.With the matrix size arises,however,the latency of the sorting process becomes more obvious and even plays a predominant role for the overall latency.To address it,this paper proposes a group sorted MGS(GMGS)algorithm,which predictably selects more than one columns at once so that the following decomposition process can be performed directly,without waiting for a new column.In addition,the GMGS algorithm converts the complicated division and square root operations to rather simple multiplications,therefore,this algorithm exists more friendly for hardware imple-mentation.To test the side effects of the predictable sorting process on MIMO detection and LR complexity.The GMGS algorithm is adopted as a preprocessing algorihtm in an uplink MIMO simulation system.Various MIMO detectors are employed and differ-ent numbers of antennas are also configured in this simulation.Results indicate that the GMGS algorithm has negligible effects on MIMO detection performance and LR com-plexity while optimizing the latency.More importantly,this latency reduction becomes more efficient for larger-sized matrices.Therefore,the proposed GMGS algorithm can suit well with future MIMO systems.Based on the GMGS algorithm,two correspond-ing hardware architectures are also proposed for 16×16 MIMO system.highly pipelined architectures are employed,and hardware reused is adopted.Synthesis results indicate that the processing latencies are respectively 0.32 us and 0.26 us,superior to other similar designs.Although the above GMGS algorithm has an excellent latency performace,its through-put and area is relatively inferior,which impedes its application in high data-rate sce-narios.To address it,this paper proposes a sorting-relaxed GR(SRGR)algorithm for MIMO systems,which is superior in terms of latency,throughput,area,and flexibility.The SRGR algorithm is based on the GR algorithm,and the highly-pipelined CORDIC algorithm is employed to realize high throughput and low area.To alleviate the latency problem caused by CORDIC chains,the SRGR algorithm adopts a relaxed sorting strat-egy.This strategy can selects multiple columns at once so that the element elimination can be paralleled in two levels.Moreover,l~1-norm is adopted to substitute the tradi-tional l~2-norm,which can decrease the complexity further.Based on this algorithm,the corresponding hardware architecture is also proposed for 16×16 MIMO system in this paper.This architecture adopts a configurable CORDIC scheme,which can work in both vector mode and rotation mode.Thus the diagonal elements and non-diagonal elements can be processed with the same CORDIC unit to avoid data switching.Benefiting from the relaxed sorting strategy,the idle clocks are notably reduced,helping this architecture realize low latency.Finally,this architecture is implemented with a 65nm CMOS technol-ogy,and the synthesis results are compared with the state-of-art designs.The comparison indicates that the SRGR architecture outperforms other designs in terms of the latency,throughput,area,and area efficiency performance.The LR technique is widely utilized in MIMO detections,which can effectively im-prove the detection performance or decrease the complexity of MIMO decoders within the same performance constraints.LLL algorithm is one of the most famous LR algo-rithms,which can always find a near-optimal base for the same lattice.However,the LLL algorithm suffers from low area efficiency because the column swap does not hap-pen in every iteration,and this problem goes even more serious for larger-scale MIMO systems.To address it,a parallel greedy LLL(PGLLL)algorithm is proposed in this pa-per,which only performs the iterations with column swaps.Compared with the existing greedy LLL algorithms,the PGLLL algorithm adopts a paralleled scheme in which each stage is divided into independent iterations.Therefore,multiple iterations can be selected at one stage to enhance the convergence.Moreover,a novel selection criterion is de-signed in the PGLLL algorithm,which comprehensively absorbs the low-complexity and high-efficiency benefits from the traditional criteria.Software simulation indicates that the PGLLL algorithm can achieve a near-LLL performance within 6 stages whereas other greedy LLL algorithms need dozens or tens stages,so the PGLLL algorithm is potential to decrease the latency.In addition,the PGLLL algorithm only process 2 iterations at a stage for 16×16 MIMO systems,whereas the non-greedy LLL algorithms would process 8 iter-ations within the same algorithm scheme.So,this algorithm is also potential to decrease complexity.Based on the PGLLL algorithm,the corresponding hardware architecture is also proposed and implemented in 65nm CMOS technology.Results indicate that the PGLLL architecture has a great predominance in throughput and latency performance.