Research On The Design Of Memristor And Memristor-based In-memory Computing

Over the past few decades,advances in information technology have mainly relied on the scaling of silicon-based semiconductors to improve performance of devices,chips and systems.However,with the failure of Moore's law,traditional silicon-based semiconduc-tors are coming to the end of reducing feature sizes to improve device performance.At the same time,the computing system based on the Von-Neumann architecture is plagued by"memory wall","power wall" and other problems,which the slows down performance improvement.In order to break the bottleneck of traditional computing system perfor-mance improvement,the future computing system must be comprehensively innovated at the device and architecture level.Memory with higher performance,brain-like computing and in-memory computing are considered as the future computing solutions.Memristors are expected to play an important role in these research areas.In this paper,the principle,design,preparation and characterization analysis of binary and multivalued memristor de-vices are studied,and high-performance memristor device design and preparation schemes are provided.Based on binary and multivalued memristor devices,new in-memory logic calculation and neural morphology calculation methods are designed respectively.The main work of this paper is as follows:The second chapter summarizes the memristors performance requirements of in-memory logic computing and studies the design and preparation process of Cu/a-Si/a-C/Pt binary memristor devices.At last,it verifies the performance of binary memristors by means of characterization.The first section of this chapter firstly introduces the re-search status of memristor-based in-memory computing and summarizes the performance requirements of memristor-based logic calculation.The second part introduces the device design process by analyzing the mechanism,material and structure of the device.Then,it introduces the device preparation process and process control,and evaluates whether the device conforms to the design expectation by means of microscopic characterization.The third part is about the electrical characterization of the device and it mainly focuses on the study of the device resistance and switching voltage uniformity,switching speed,durability,retention characteristics and resistance value drift and other characteristics.The third chapter proposes the direct resistance coupling logic calculation method and designs the basic logic,the derivative logic,the logical cascade and the parallel oper-ation method.Based on the work,we operate the Boolean logics and the arithmetic opera?tion efficiently.In the first section of this chapter,the direct resistance coupling principle is proposed,the basic logic,derivative logic and logical cascade method are designed and 16 Boolean logics are realized.The second section studies the parallel calculation method of memristor logic calculation based on the direct resistance coupling principle and proves the feasibility of parallel calculation in single R arrays through simulation and actual measurement respectively.In the third section,through the combination,cascad-ing and parallel configuration of memristor logic gates,a one-bit full adder and a partially parallel multi-bit full adder are realized.At last,the performance is compared with other published research results.In chapter four,the performance requirements of memristor devices for neural com-puting were analyzed and summarized.The design and preparation of Pt/C/NbOx/TiN memristor planar cross array and three-dimensional vertical array were studied,and the performance of multi-value memristor devices was verified by characterization.The first section of this chapter firstly introduces the current research status of memristor-based neural computing and summarizes the performance requirements of memristor devices.The second part introduces the design process of the device through the analysis of the mechanism,material and structure of the device.Then,it introduces the preparation pro-cess of the planar cross array and three-dimensional vertical array of the device.The third part is mainly about the electrical characterization of the device.It focuses on the study of the device's self-rectifying,synaptic plasticity,nonlinear of conductivity adjustment,durability and retention characteristics.In chapter five,the method of weight mapping in memristor array is studied.Based on the device characteristics,a fast and accurate read-write strategy of the self-rectification memristor array is designed.In the first section of this chapter,the methods of bilayer pulsed neural network weight mapping in planar cross array and three-dimensional con-volution neural network weight mapping in three-dimensional vertical array are studied.The functions of two-dimensional and three-dimensional vector matrix multiplication are realized respectively.In chapter 2,an adaptive segmentational conductance adjustment method is studied for weight adjustment of self-rectifying array,and the writing error caused by this method is analyzed.This paper studies the weight reading method in the self-rectifying array and analyzes the reading error.Further,it studies the relationship among the reading error,array size,device position,device conductance state and device rectifier ratio,which provides the foundation for the system simulation.In the third sec-tion,MINIST classification is realized by simulation based on planar memristor array.It has faster training convergence rate and higher recognition rate compared with other works.The three-dimensional convolutional neural network is realized by the simulation based on three-dimensional self-rectifying memristor's vertical array.The identification and classification of three-dimensional samples are completed.The classification results are compared with the ideal situation with no weight error and the influence of non-ideal characteristics of devices on the network performance is analyzed.