Research On Key Technologies Of SMT Processors For Data Center

In order to improve the utilization of processor(CPU)resources in data centers,the Simultaneous Multithreading Technology(SMT)that can run multiple threads on the same processor has been widely adopted.However,SMT will cause competition between hardware threads for shared pipeline resources in the same processor,resulting in unpredictable performance fluctuations and a poor Quality of Service.In addition,the operating environment where same physical resources are shared by multiple applications can easily cause security issues.The fine-grained shared resources in SMT processor provide more potential targets for attackers.Therefore,how to provide performance guarantee and security assurance for SMT processors in data center application scenario is not only a research hotspot in academia,but also a challenge faced by the industry in practical applications.Aiming at the urgent problems of SMT processor in the data center,this thesis studies the requirements of Quality of Service guarantee and security assurance of SMT processor.The main research contents and contributions are as follows:1.Investigate the root causes of fluctuations and unpredictability of SMT processor performance.This thesis adopts the methods of real machine test and processor simulator simulation respectively,selects the standard benchmark SPEC CPU2006 as the workload,and focuses on the experimental analysis of the relationship between processor performance and pipeline resources.First,using a variety of existing resource allocation strategies to evaluate their effects on reducing performance fluctuations,it is found that the performance fluctuations of modern SMT processors come from incomplete resource isolation;secondly,by analyzing the sensitivity of application performance to the number of pipeline resources,it is found that the nonlinear relationship between pipeline resources and performance determines that the static resource partitioning strategy cannot provide predictable performance guarantee;finally,through the analysis of the relationship between pipeline resources,workloads,and performance,it is found that each resource may become a potential performance bottleneck,and a set of SMT workloads will compete with multiple resources at the same time.The above findings provide a solid foundation for this Quality of Service guarantee design.2.In order to accurately quantify the performance degradation caused by competition for shared resources,a shadow clock counting mechanism based on shadow queues is proposed.The shadow queue can identify the pipeline blocking event caused by other threads competing for shared resources by simulating the resource usage when a target thread would execute alone during the simultaneous execution of the target thread and other interfering threads.Based on identification results,the shadow clock counting mechanism can predict the ideal execution time of the target thread in real time by classifying and counting execution cycles.Qo SMT is implemented based on GEM5,and evaluation results based on 24 pairs of SMT workloads show that this mechanism is accurate in predicting performance,with an average IPC prediction error of 0.069.3.In order to provide accurate and predictable performance guarantee for the target thread,a resource allocation strategy combining software and hardware is proposed.First,a software interface is designed through which the administrator or user can directly pass the performance expectation of the target thread to the underlying hardware.Secondly,in order to ensure that the performance of the target thread meets the expected target,a dynamic resource allocation strategy based on loop feedback control is designed.In each phase of target thread execution,in order to meet the resource requirements of the target thread,the strategy dynamically and real-time adjusts the pipeline resource allocation according to the performance expectation target,resource competition degree,runtime performance and ideal performance prediction value.The performance evaluation results show that the ability of this strategy to guarantee performance is significantly better than existing related strategies.When the target expectations are set at 85%and 90%,the average control accuracy error is 1.4% and 0.5%,respectively.4.In order to prevent attackers from using shared cache resources to implement transient execution attacks,a set of defense mechanisms based on security shadow tags is proposed.First,referring to the shadow tag used for performance guarantee,add a security identification label to the memory access request of the secure thread,so that the shared cache can distinguish cache requests from different threads.Secondly,based on the security label,the security isolation of the "hit" and "replacement" cache operations of the secure thread can be achieved,which can make speculated memory access instructions from the secure thread directly modify the cache state with reducing performance overhead.Finally,a new transient execution cache is designed for the existing processor cache path,which is used to restore the original cache block evicted by the secure thread under the wrong prediction path.By combining these two defensive designs,it is ensured that the modification of the shared cache by the secure thread is not visible to the attacker.Security analysis and experiments show that this mechanism can prevent the leakage of confidential data.Compared with other existing security designs,this mechanism has the smallest performance overhead which only has an impact on execution time of 3.9%.In summary,aiming at the Quality of Service and security issues faced by SMT processors in data centers,this thesis reveals the causes of performance fluctuation of SMT processors fundamentally,and proposes an innovative resource allocation mechanism for SMT processors in data centers,which can provide stable and predictable performance guarantee for threads with Qo S requirements.At the same time,an innovative hardware security mechanism based on security label is proposed,which successfully eliminates the transient execution attack against SMT processor,and provides reliable security for the security-sensitive thread.