On-Chip Coplanar Waveguide And Its Applications

With the continuous rapid development of microwave and millimeter-wave monolithic integrated circuits, Coplanar Waveguide (CPW), as one of the important microwave planar transmission line, has attracted a lot of interest. The CPW offers several advantages over conventional microstrip line: simpler fabrication; symmetric structure; easier shunt as well as series surface mounting of active and passive devices; elimination of the need for wraparound and via holes; no limitation of size reduction etc. As a result, CPW is widely used in the integrated circuit of microwave, millimeter-wave, high temperature superconducting (HTS) area, such as millimeter-wave amplifiers, active combiner, mixer, HTS filter and printed antennas. Onchip CPWs have attracted a lot of attention in high-speed circuits. For instance CPWs are often used for timing adjustments in high-speed digital circuit designs, resonators (for negative index materials), miniaturised electromagnetic band-gap structures, filters and delay lines (for high-speed analogue-todigital converters).On-chip transmission lines (TLs), especially CPW, are essential for the design and analysis of highspeed interconnects and circuits. Their characterisation and modelling have attracted a lot of interest. It is now well known that on-chip CPW has different characteristics than off-chip CPW due to the conductive silicon (Si) substrates, the limited metal film thickness, and dielectric layer (e.g. silicon dioxide) thickness. In this dissertation, the theory and experimental analysis of the CPW characteristics and modeling technology have been studied in depth; several key technologies of the on-chip CPW applications have also been investigated.First, among various analysis methods for conventional CPW, the comformal mapping method is the simplest one, it provide a close expression of the propogation parameters of various types of CPW structure. In the conventional comformal mapping analysis of CPW, the thickness of the metal was always neglected. In this thesis, CPW with finite metal thickness is analysed and the characteristic parameter expressions is derived using comformal mapping method.Second, although CPW is widely used on-chip, but the characteristic research are mainly focused on straight CPWs, in addition, transmission line bends are often needed due to layout routing considerations and chip area limitations, especially the CPW bends characteristics on the silicon substrate have not been reported. A compact and computer-aided-design-(CAD)-oriented RLCG (resistance, inductance, capacitance, and conductance) model is presented, the optimal miter band selection is given, which can be used in the meandered CPW design and circuit analysis. Both simulation and sample test results show that, compared with the straight CPW, the on-chip mitered meandered CPW has higher characteristic impedance due the bigger inductance and smaller capacitance, has bigger transmission parameter in frequency domain and bigger signal amplitude of time-domain measurement. The optimal miter value selection should base on the line characteristic impedance matching condition.Third, a new permittivity measurement method is presented which is based on the on-chip CPW with finite metal thickness. In certain situations, the volumn of the material under test (MUT) itself is very small, such as the microfluid, solution or cells, also not easy to fix on top of the metal lines. In this thesis, the MUT is proposed to place into the slot line between the signal line and the ground line of the CPW, which is also considered to be the strongest field distribution area of the CPW. Therefore the PDMS walls or the microfluid channel is not required and the permittivity measurement sensitivity will be significantly enhanced, in addition, the volumn of the MUT can be adjusted by tuning the thickness of the metal. The validity of this approach is validated by the simulation using HFSS simulator. The calculated permittivity values agree well with the expected values, especially in the case of the thickness is comparable with the slot width, the simulation errors are less than 10%.Fourth, measuring dielectric property changes has been developed and used as an effective approach to investigate biological matter and processes, such as protein thermal unfolding and refolding, lipid bilayer membranes, and cells. Measuring the change of the propogation and reflection parameters (including amplitude and phase) to obtain the permittivity is the basic principle of those traditional permittivity measurements. However the sensitivity of these approaches is relatively limited due to the strong background signals, especially when the change of the MUT permittivity is very weak, the tiny change of the propogation parameter is very hard to capture. Therefore a cancellation type of permittivity variation observation measurement based on on-chip CPW is presented. In this scheme, the extent of the cancellation from two signal ways reflects the MUT changing process, that is, to analyse the big variation information from weak signals, not the traditional small variation information from strong signals. This device is composed by two Wilkinson power dividers, one way of the divider is the reference signal while the other is the MUT signal. In addition, the MUT is placed in the slot which is the most sensitive place of the CPW, significantly enhanced the variation information of the cancellation from the two signals. The simulation results show, compared with the traditional single CPW measurement, the S21 magnitude sensitivity of this cancellation type on-chip CPW-based dielectric parameter variation measurement proposed in this thesis can be improved by 8dB-27dB.Fifth, high voltage and high power electrical pulses are required on-chip for high performance system-on-chip (SOC) development, such as, cell analysis, ultra-wide band (UWB) communications, and terahertz pulsed technology, and pulse-forming-line (PFL) based on-chip pulse generation circuits are promising to extend the high speed short pulse generation capabilities of standard complementary-metal-oxide-semiconductor (CMOS) devices and circuits. In this thesis, the PFL based pulse generator which was used in the traditional pulsed power technology is first implemented in the standard CMOS technology, the on-chip meandered CPW is used as the signal transmission line. Five different short pulse generation circuits are compared and analysed through the schematic and layout simulations of Cadence. Test samples are fabricated in IBM CMOS 8RF_DM 0.13?m technology. Both simulation and measurement results validate the possibility of the on-chip short pulse generator based on the traditional PFL technology. Pulses of ~160ps durations and 120 mV-400mV amplitudes are obtained from the on-chip CPW based PFL circuits discussed in this thesis when the power supply is tuned from 1.2V to 2V in the measurements.Sixth, on-chip systems such as in the CMOS technology, based on the reliability considerations, the supply voltage is limited, therefore the amplitude of the output short pulse generated on-chip is limited. To further increase the amplitude of the output short pulses, three different options (tapered CPW, Marx type transmission line transformer, stacked Blumlein circuit) are discussed in this thesis. Studies have shown that in order to obtain the same width, same amplitude pulse, the Marx type transmission line transformer and stacked Blunlain circuit occupy double size of the tapered CPW way, the later one is more suitable in the on-chip circuit design.