Research And Design Of High Efficiency Linear Audio Power Amplifier With Adaptive Supply Rails

Modern portable electronics incorporate hands-free operation, MP3 music playback and DMB reception, leading to a demand for highly integrated and power efficient audio amplification. Class D audio power amplifiers have the overwhelming efficiency advantage over other kinds of audio amplifiers at the cost of slightly reduced performance and a level of switching noise, which might, in some cases, interfere with RF functions such as mobile phone, GPS or FM radio reception. Traditional class AB amplifiers, which are still largely used, are not suited to meet high efficiency demand. The high efficiency linear audio amplifiers with adaptive supply rails are introduced to bring together the benefit of class AB and class D. These new kinds of high efficiency linear amplifiers, whose supply rails are adaptively changed according to the magnitude of the output audio signal, are developed to improve the power efficiency, reduce the power dissipation and component size. These amplifiers have also good audio quality and less of EMI since the output stage adapts class AB operation. Then research and design of low cost, high efficiency and high fidelity linear audio power amplifiers are largely required both in industry and academe.There are two kinds of high efficiency linear amplifiers designing in this thesis. One is the class G audio amplifier which has discrete adaptive power supplies. The maximum average efficiency depends on the amplitude distribution of the input signal and the supply voltage transition points. The proposed class G audio amplifier has three blocks:adaptive power supply, signal processing block and bridge-tied class AB amplifier. Through the research of audio signal amplitude distribution, a three mode charge pump is introduced to produce adaptive supply rails for class G audio power amplifier. According to the amplitude of output signals, the charge pump has three level output voltages available to save power. It operates both in current mode at high output load and in pulse frequency modulation (PFM) at light load to reduce the power dissipation. Also dynamic adjustment of power stage transistor size based on load current at PFM mode is proposed to reduce the output voltage ripple and prevent the switching frequency from audio range. Since the class G audio amplifier has only positive supply rails, a nonlinear signal processing is introduced to optimize the power dissipation on the ground side. An obvious advantage of the proposed technique is that it can be easily integrated on the same die with the other blocks at base band processor using a low cost single well CMOS process. The circuit has been designed and fabricated using SMIC 0.18-?m 3.3V single well CMOS process. The measured results show that it obtains less than 0.1% THD+N with a 1 KHz sine wave signal. Measured efficiency of class G is much higher than traditional class AB amplifier at the low power range which means it is suitable for audio amplification since the most power of audio signals are concentrated at low level range.The other kind of high efficiency linear audio amplifier is Class I amplifier which changes the supply voltage continuously according to the amplitude of output signal. A single phase power supply class I linear audio amplifier system architecture is proposed according to the characteristics of the audio signal, and then the efficiency of this audio amplifier is derived. To optimize the power dissipation of both PMOS and NMOS power transistors with positive adaptive power supply, variable gain signal processing circuit is designed. The power converter employs buck structure and can operate in PWM and PFM mode to save power according to the load current level. When the current load is heavy, the buck converter operates in PWM mode and the output changes along with the audio signal. The average current feedback is introduced in voltage feedback loop to widen the loop bandwidth. An improvement of DC-DC Buck PWM controller is made to solve the pre-phase problem. The circuit has also been designed and fabricated using SMIC 0.18-?m 3.3V single well CMOS process.The measured THD+N is better than 0.07% when output power is lower than 360 mW with a load of 8?and the maximum efficiency is about 82%. When output power is lower than 90 mW, the efficiency is improved up to 70% comparing to class AB. A theoretical efficiency calculation demonstrates a reasonable agreement with measured results.