Associative Computing with Resistive Memorie

Power dissipation and memory bandwidth are significant performance bottlenecks in virtually all computer systems. Associative computing with ternary content addressable memories (TCAM) holds the potential to address both problems in a wide range of data intensive workloads. Power dissipation is reduced by eliminating instruction processing and data movement overheads present in a purely RAM based system. Bandwidth demand is lowered by processing data directly on the TCAM chip, thereby decreasing off-chip traffic. Unfortunately, existing SRAM-based TCAM cells are over 90x larger than a DRAM cell at the same technology node, which limits the capacity of commercially available TCAMs to a few megabytes.;This dissertation first examines the integration of gigascale TCAM systems based on resistive memories within a general purpose computing platform. TCAM density is improved by novel, resistive memory cells that exploit phase change and spin-toque transfer magnetoresistive RAM technologies. TCAM chips are organized into a DDR3-compatible DIMM, and are accessed through a software library with zero modifications to the processor or the motherboard. Leveraging associative lookups by the memory circuits and a set of integrated, programmable microcontrollers that execute user-defined kernels on the search results, the proposed TCAM systems achieve average speedups of 4-4.2x and average energy reductions of 6.5-8x as compared to a conventional RAM based system.;The dissertation second presents the case for a database processing unit (DPU) that significantly improves the energy efficiency in big data analytics. The DPU augments a general-purpose processor with 1) an STT-MRAM based scratchpad memory that implements a CAM cell with a 2.45x higher density than an SRAM cell, and 2) an enhanced DMA unit that facilitates the transportation of data between the CAM and memory subsystem. By mapping the relational database operators to the CAM circuits, columns of data are processed directly on the CAM chip in a vectorized manner. This eschews streaming the entire data set in and out of the processor pipeline, and significantly reduces the performance and energy overheads caused by the data movement.