| A computer system is the collection of many subsystems which interact with each other to accomplish the desired computing tasks. Each subsystem (hardware/software) can be further divided into several modules. Depending on granularity, the process can continue to lower levels recursively.; In most levels, the computing process can be viewed as selecting an object from several possible candidates and then executing the predetermined activity upon it. This dissertation addresses the problem of selection verification and proposes a formal model for verifying the selection process. The methodology of achieving this is to give the capability of identity checking to the called objects. The called object is "active" instead of "passive" in the sense of selection verification. Different mechanisms and measures should be chosen at different levels to make the called object to be active in selection verification process.; The principles and requirements of implementing the verification process are discussed. It can be implemented at various levels, from hardware, firmware, up to the system software. Several examples have been included to demonstrate the possibility and feasibility of the design methods for the verification process.; A concurrently testable microprogrammed control unit was designed using this model. As external information is included in the signature checking, the correct routine selected is verified as well as the control flow sequencing inside the routine. The machine program level control flow monitoring is desirable. A new technique for concurrent testing of the instruction sequencing within a block and correct branches among blocks is presented. A procedure for selecting the optimum syndrome space compression is given. This data reduction technique can be used to increase the efficiency of signature verification techniques.; Reliability is one of the major concerns of computer systems. Since selection verification is an effective way for error detection with possible low error latency, the schemes for selection verification at different levels can be designed to coordinate with the fault tolerance techniques as error detection, damage confinement and error recovery, with a view to optimize the system availability and reliability. |
