FDCT PROCESSOR AND HYBRID CODING OF BROADCAST COLOR TELEVISION

Through mathematical analysis and software simulation, an efficient hardware structure for a FDCT processor is developed. The processor has throughput rates compatible with processing standard NTSC signal sampled at 10.7 MHz. It is capable of processing 4- or 8- or 16-point input segments and can also be used as a part of a larger system which processes a 32-point input segment. The prototype consists of three high speed computational modules and a versatile control mechanism which enables the modules to operate in parallel. The symmetrical structure of the computational modules allows the basic hardware design to be used for inverse FDCT processing. A two-stage pipeline structure permits the processor to be realized using TTL-technology.;The FDCT processor is used to develop a hardware feasible architecture for hybrid DCT/DPCM coding of color television signals. The coding system is based on transforming (4 x 4)-pixel blocks and reducing inter-block correlation by using adaptive DPCM. An adaptive coding is also used to reduce bit rates for transmitting high quality color video signal via a 44.7 Mb/s carrier system.