Design and simulation of a wafer scale integration magnetoresistive memory architecture

Magnetoresistive memory has been identified as a viable candidate for water scale integration. Water scale integration requires an architecture which tolerates defects with redundant elements. A wafer scale architecture with multiple levels of redundancy is designed for magnetoresistive memory. Yield models which consider multiple types of defects and defect clustering are used to calculate module and wafer level yields. The yields of various redundancy combinations are simulated to optimize the architecture for current semiconductor manufacturing processes. The optimized redundancy has six spares at the 16 Kbit module level and two spares at the 1 Mbit module level. This architecture yields a capacity of over 250 megabytes for all the statistical processing distributions considered in the simulation. The areal cost of the redundancy is less than 10 percent.