| Present audio applications are requiring an increasing amount of digital signal processing (DSP) capability, while the power budgets for those applications are being reduced. Issues impacting power consumption of a custom VLSI DSP include algorithm, architecture, number representation, logic design, geometric layout, and process technology. Two of these issues, namely processor architecture and number representation, were considered in developing estimates for the power dissipation of an arithmetic unit, memory, control, and intrachip communications, the four basic elements required for a single chip VLSI digital signal processor. We compared the power dissipation of DSP performed using uniformly encoding with that using logarithmic encoding and showed that the power dissipation of uniformly encoded signal processing can be as much as twice that necessary for the same signal processing using logarithmic encoding, with a comparable dynamic range and signal to noise ratio. We also determined that uniform processors can require as much as 50% more silicon area than their logarithmic counterparts. Estimates were developed for the power dissipation of two parallel architectures, a pipelined system and a bused system, from which we determined the degree of parallelism needed to minimize the DSP system's power dissipation, and found that the degree of parallelism is a function of the architecture, choice of number system, and word length. For the parallel architectures, we also found that arithmetic functions followed by control account for the bulk of the power dissipation, and that the memory's contribution to power dissipation decreases with increased parallelism. Finally, we considered a fully custom logarithmic processor and compared it with a comparable logarithmic system. While the logarithmic design using some dynamic logic requires comparable energy to the uniform system, replacing the dynamic logic with fully complementary logic provided a 29% decrease in total power consumption. |
