| The power-handling capability of power MOSFETs is beginning to rival bipolar transistors. This new capability is based on the use of double-diffusion techniques to achieve short active channels and on the incorporation of a lightly doped drift region between the channel and drain contact, which largely supports the applied voltage. In this work, quantitative models for on-resistance are developed for the three most commonly used structures--the LDMOS, VDMOS, and VMOS. These models are useful in optimizing a particular device and in comparing all of them for a specific application.; Small surface spacings and geometries in the VDMOS result in two-region saturation I-V characteristics that can be explained in terms of the depletion of the epitaxial region between channel junctions. A first-order I-V solution demonstrates the dependence of this phenomenon on the physical structure. The degradation of this effect on device transconductance can be more severe than thermal effects in high-current operation.; Breakdown limitations and parasitic bipolar latchback are examined in detail and are related to device structure and processing. The switching requirement dV/dt during turn-off places a severe constraint on channel thickness and doping concentrations under most layout conditions. The punchthrough limit dominates only when the channel contacts are adjacent to the edges of the gates. The differences in performance and on-resistance between power-MOS and bipolar devices are studied in terms of carrier injection and transport mechanisms.; Knowledge of electron mobility in both inversion and accumulation layers is essential for accurate modeling of power MOSFETs. This need resulted in an extensive set of mobility measurements as a function of various processing parameters. Analytical expressions are derived to predict mobility over a wide range of conditions, and the result will have significant impact when optimizing the performance of all types of MOS structures. |
