Physical model enhancement and exploration of bandgap engineering in novel sub-100nm pMOSFETs

This work involves physical model enhancement in a new device simulation platform, MINIMOS-NT, and a study of the applications of bandgap engineering in novel sub-100nm pMOSFET design. Less cost, better performance and continuous scalability have been the driving force for the rapid development of semiconductor technologies. Because of the great challenges in Si CMOS scaling, developing new materials and new device structures is important. In the course of searching possible solutions, various strained Si/SiGe heterostructures were investigated in this work, by both computer simulations and experimental characterization. While drift-diffusion and hydrodynamic simulations were mostly used in the work, Monte Carlo simulations were performed whenever it was necessary, in order to gain better understanding. The experimental work validates our simulation results. Although some device structures, such as graded SiGe channels and source-side energy steps are found to be counter-productive in improving drive current, the analyses of the results provide us more insights into device physics in the deep submicron regime. The use of strained SiGe in the source and/or drain did show the advantage of reduced short-channel effects, one of the greatest problems of the device scaling beyond 100 nm. The drawback of such devices is the degraded drive current due to the hetero-barriers in the channel. This obstacle can be overcome by using a thin Si or SiGe cap, where the current flows without passing through the hetero-barriers. Finally, a novel pMOSFET with a SiGe source/drain and a Si/SiGe/Si quantum well channel is proposed, which is called a high mobility heterojunction transistor (HMHJT). Higher drive current due to mobility enhancement in a strained SiGe channel and suppressed short-channel effects due to the band offset between the source/drain and the bulk are predicted. Compared to realistic, conventional Si devices, HMHJTs have improved device performance and scalability for various circuit applications, such as low standby power/leakage, and low operating power applications.