Technology development and process integration of alternative gate dielectric material; hafnium oxide

In this work, the processes to deposit ultra-thin hafnium oxide and thermally stable TaN electrode have been investigated and dielectric properties of hafnium oxide have been examined in detail to show CMOS process compatibility. All the technologies developed in this work have been integrated to fabricate TaN gate MOSFETs with a gate dielectric of equivalent oxide thickness (EOT) less than 10Å.; Control of interfacial layer growth and post-dielectric deposition heat cycle were found to be critical factors in the electrical thickness scaling of hafnium oxide. With RTA reoxidation process, the EOT of hafnium oxide could be scaled down to 8Å. Leakage current was kept well below 1A/cm 2 even at 8Å range. Other dielectric properties such as hysteresis, dispersion, interface state density and reliability have also been investigate and found to be promising. Proper post deposition anneal was a key step to reduce hysteresis and interface state density. Forming high quality interfacial layer was crucial to improve the reliability characteristics.; In general, there is a trade off between the EOT of hafnium oxide and its dielectric properties. TaN electrode and NH₃ nitridation process turned out to be the breakthrough technologies to improve this trade-off for optimized device performance. Since TaN electrode provided an excellent diffusion barrier, the EOT of TaN/HfO₂ could be kept around 10Å even after all the heat cycle to fabricate transistor. Surface treatment using NH₃ nitridation generated a passivation layer that further improved the thermal stability of TaN/HfO₂. The reliability of TaN/HfO ₂ was drastically improved after NH₃ nitridation.; Thus, based on these progresses in the unit process, TaN MOSFET was successfully fabricated and evaluated. Different process flows with different heat cycle such as self-aligned process (higher thermal budget process) and non-self aligned process (low thermal budget process) were used to investigate the difference between conventional CMOS process and replacement gate process. Excellent electrical characteristics (e.g. S ∼ 68mV/dec) and reliability characteristics (e.g. high E_BD, low charge trapping and SILC) were also obtained. This result indicate that HfO₂ combined with proper metal electrode can extend the gate dielectric scaling trends down to 50nm technology node, especially with replacement gate process.