Performance analysis of asynchronous packet-switched bus-based multiprocessor systems

The purpose of this work is to analyze the performance of asynchronous packet-switched bus-based multiprocessor networks. With the advent of optical buses and ease of implementation of cache coherence schemes, bus-based systems are still being implemented commercially. A new bus-based architecture is presented which is much more easily expandable than existing bus-based systems. It was found that its system power exceeds those of existing bus architectures mainly attributed to a reduced number of connections per bus. The analysis begins with the infinite buffer model and thereafter the finite-buffer model is presented, the results have been validated against extensive simulation. This then leads to the optimal utilization of resources and determination of the optimal bus and memory allocation strategies, and buffer lengths at the different bus and memory subsystems.;The mean value analysis technique is used to evaluate the design parameters of the infinite-buffer networks but this method does not apply to finite-buffer networks because there is a possibility of the packets being rejected due to insufficient buffer space, instead a modified queueing model is used. A Poisson arrival distribution and a deterministic service time distribution is incorporated. From the previous analysis given for the M/D/1/L queue, an approximate closed-form solution for the M/D/c/L queue is derived, the results of which are shown to be within acceptable limits for most practical applications. Different analytical models are discussed and the best in terms of lower complexity and lower computation time is given. A more realistic simulation model is used with all practical implementations considered. The analysis applies well to both single-level (UMA), hierarchical (NUMA) networks and ATM networks.;A new deadlock free packet-switched cache coherence protocol for bus-based systems is shown which is in some ways more efficient than the SCI protocol. This protocol can quite easily be adapted to bus-based hierarchical networks as well.