Advanced clock recovery techniques for high-speed packet-switched optical networks

Wavelength-division multiplexing (WDM) optical networks increase signal bandwidth by allowing the transmission of multiple high speed channels simultaneously through the same fiber while packet-switching allows the integration of a wide range of broadband services. All-optical WDM packet-switching is envisioned as the communication framework for future broadband networks. Implementation of WDM packet-switched networks requires efficient solutions for several synchronization problems.;When an optical receiver is switched from one wavelength to another, the continuity of the bit streams between adjacent packets is disrupted. Since it is impossible to guarantee the same bit clock alignment for all the received packets, every receiver must be able to perform a new bit clock recovery for every received packet. The clock alignment must be completed in a small fraction of the packet duration to minimize the wastage in transmission capacity. Conventional PLL-based circuits are inadequate because they require thousands of bits to lock on.;Two practical bit synchronization techniques for clock recovery on a packet-per-packet basis are (i) embedded clock transport (ECT) and (ii) delayline phase alignment (DPA). In the embedded clock transport scheme, the clock recovery is performed by explicitly transmitting the clock tone along with the packet. The clock tone is placed exactly at a notch of the data spectrum, and therefore, relatively low interference from the data signal occurs. At the receiver, a narrow bandpass filter extracts the clock tone which is then used for data sampling. This clock recovery scheme is demonstrated at 2.488 Gbit/s using off-the-shelf components. The delayline phase alignment scheme uses a parallel oversampling technique to reliably recover the bit stream with digital circuitry. A multi-tap delay line and a smart selector are used to align the received bit stream with the local clock. The DPA logic monitors the bit transitions during a preamble sequence and determines the optimum sampling tap. Substantial signal processing, including bounce suppression and transition position averaging, is required to reduce the effect of noise and waveform distortion. An experimental prototype using fast PLDs operates at 80 Mbit/s.;ECT and DPA are used in the implementation of an all-optical packet network prototype. ECT is used for recovering the bit clock of ATM-size data packets (424 bits) at 2.488 Gbit/s in 40 bits with an optical power penalty of 1 dB while DPA recovers the bit clock of control packets at 80 Mbit/s in 4 bits also with a 1 dB optical power penalty.