| Frame synchronization, multiplexing and error detection are three basic issues in Synchronous Digital Hierarchy (SDH) transmission networks. The relative techniques are required for meeting efficient and correct digital signal transmission in high speed digital communication networks. According to a group of ITU-T recommendations G.707, G.708 and G.709, this dissertation deals with research on the basic issues of frame synchronization, multiplexing and estimation of errored block detection for STM-1 system with a rate of 155.520 Mbits/s in SDH networks. In this framework, first, we present an entirely novel parallel processing-based frame synchronization system and analyze its performance. By using a parallel approach, we are able to process in SDH system at a rate of 19.44 MHZ. This means that all functions, such as descramble, section overhead monitoring, pointer processing, etc., are operated at byte rate after the framer. All of these functions must be done on a byte wide basis. Thus all operations are performed in parallel in an SDH processor. The scheme is expected to relax operating speed requirements and simplify complexity of the circuits used in the system. The proposed methodology can be implemented using off-the-shelf low-rate integrated circuits (ICs) without sacrificing performance. In the second part of this dissertation, we present a method for multiplexing C-3 pay-load in the STM-1 structure. Our technique eliminates signal rate variations, which occur in various multiplexing structures in the SDH networks, by using a buffer. Calculations related to the buffer capacity for C-3 payload are also presented. In the third part of the dissertation, we study bit interleave parity (BIP) code performance, find a close form to solve the probability of undetected error, and give a group of curves for estimating errored block rate. This work is based on the features of BIP code.; Although our study is based on the STM-1 frame structure, the proposed methodologies are expected to be efficient solutions for implementing other STM-N systems. |
