An SOI-based, fully integrated fabrication process for high-aspect-ratio microelectromechanical systems

A low-cost, SOI-based, fully integrated fabrication process for high-aspect-ratio MEMS has been developed and demonstrated. The fully integrated SOI MEMS process uses only two MEMS masking steps plus a standard foundry CMOS process to form sensors and actuators with on-chip electronics. The test vehicle for this process was a 50μm tall, in-plane, linear accelerometer with Σ-Δ force balanced, capacitive sense electronics. The accelerometer had 25 μG/$Hz$ noise floor and +/– 1.75 G full range.; Using a modular process approach. fully integrated MEMS devices were fabricated in three stages; trench isolation formation, foundry CMOS fabrication, and MEMS structures definition. Low cost is achieved by adding only two additional masks to a standard CMOS process: one mask for isolation trench formation and one mask for structures definition and release. The modular process allows use of inexpensive foundry CMOS, further reducing fabrication cost. In this fashion. high performance, inertial sensors can be fabricated at lower cost than comparable performance surface or bulk micromachined devices.; Separating the fully integrated SOI MEMS process apart from other SOI-based MEMS fabrication techniques is the presence of the back-filled isolation trench. The back-filled trench serves several important functions. First, the dielectric lined isolation trench provides electrical isolation between MEMS elements and the on-chip electronics, as well as isolates individual MEMS elements from one another. Resistance between isolated regions was measured at greater than 220 GΩ. Second, the back-filled trench forms a lateral anchor attaching MEMS elements to the SOI device layer. Mechanical testing on anchored structures demonstrated the anchors did not break under applied stresses in excess of 2 GPa. Third, back-fill material in the isolation trench allows embedded interconnect to run across the top of the trench, electrically connecting MEMS elements to on-chip sense electronics. Standard CMOS aluminum interconnect was used to wire together MEMS sensors and sense circuitry. Interconnect resistance of 120 /$mW/\square$ with a MEMS contact resistance of only 10 Ω/contact was achieved.; The fully integrated SOI MEMS process uses two deep reactive ion etching (DRIE) steps; one to etch the isolation trench and a second to etch the MEMS structures. DRIE is used to create 50μ tall MEMS structures with 2μ wide features. The 25:1 aspect ratio provides high sensitivity inertial sensors while effectively isolating out of plane motion modes and reducing cross-axis sensitivity.; With the ability to fabricate low-cost, high-performance, MEMS sensors with on-chip foundry CMOS, the fully integrated SOI MEMS process is a very promising technology for commercial MEMS applications.