Modeling and simulation of very-large active matrix liquid crystal display

The evaluation and control of the gate line delay time in active matrix liquid crystal display (AMLCD) is important since the diagonal of the AMLCD's thin-film-transistor (TFT) backplane is restricted by this delay. It is proposed that the gate line RC delay can be reduced considerably and the AMLCDs be made correspondingly larger, by connecting the gate line through a few via holes to a bus run on the back side of the substrate. The major contributions of this dissertation include (1) a detailed theoretical analysis and circuit modeling. The gate line connected through via holes is modeled as a modified RC transmission line that consists of a cascade of several sections of the two-port network. A mixed RC net and equivalent T ladder model is found to be an excellent approximation for the actual gate line. A top-to-back resistance ratio of ten and two via holes in each line reduce the delay from 1/7 to 1/8. (2) It is found that the voltage shift effect has important influence on the pixel characteristics and the pixel voltage drop plays an important role in the limitation of the display size of a very-large AMLCD. Appropriate RC constant, driving scheme and driving voltage have to be chosen in a good design. (3) It is also found that the gate line RC delay, the gate driving voltage, the dynamic characteristic of TFT, the driving scheme, the configuration and size of the display all have more or less effects on the uniformity of the display. Via-hole structure can improve the uniformity of a very-large display. (4) A new asynchronous driving scheme to improve the uniformity of the display is proposed.