CMOS baseband circuit techniques for integrated multi-standard wireless receivers

This work focuses on the design of the baseband filter for a multi-standard fully integrated wireless receivers. The filter is designed to meet the baseband signal conditions required by the following wireless standards: PDC, IS-54, GSM, IS-95 and WCDMA. The filter has to exhibit: a high-dynamic range, a programmable bandwidth, a precise frequency tuning feature, low power consumption and a small chip area. In addition to filtering, variable gain amplifiers (VGAs) must be employed in the baseband chain to accommodate for gain variations in the RF front-end. Limitations of the different well-known filtering techniques are investigated. New baseband filtering approaches providing improved characteristics are developed. This includes the design of a CMOS fully balanced second-generation current conveyor (FBCCII). The FBCCII is used to implement two VGAs: one is cascadable and the other provides DC offset cancellation feature. Also, a new second-order lowpass filter exhibiting a low frequency DC notch and programmable gain is presented.; Moreover, a technique for designing digitally tuned filters is proposed. The technique incorporates the R-2R ladder to provide precise frequency characteristics that can be tuned over a wide range. A sixth-order channel select filter based on op-amps is implemented. The R-2R ladders are programmed to tune the filter response which accommodates the channel bandwidths of GSM, IS-95, and WCDMA. In addition, design of a fully-integrated servo loop for DC offset compensation using the R-2R ladder is proposed.; Furthermore, a novel approach for designing highly linear digitally programmable filters based on digitally controlled current followers is presented. A sixth-order lowpass filter accommodating PDC, IS-54, GSM, IS-95 and WCDMA is implemented. Finally, a wideband CMOS current follower with robust low distortion based on current folding is proposed. The design avoids the use of current mirror(s) in the signal path to minimize the distortion caused by mismatched mirroring transistors. Statistical measurements show that the current follower with differential pair exhibits more robust and improved linearity of 5.2dB over the conventional current follower. Four different VGAs exhibiting high linearity are implemented using a fully balanced version of the current folding current follower (CFCF) and their performances are practically evaluated.