| Rapid advances in semiconductor technology have made it possible to realize the full potential for integrating on a single chip such different components as processors, memory, buses, application specific integrated circuit (ASIC) components, and mixed-signal components. The increasing heterogeneity and programmability associated with the system-on-a-chip architecture (SoC), together with the ever-increasing operating frequencies and technology changes pose great challenges to Very Large Scale Integration (VLSI) testing. Traditional hardware-based self-testing techniques such as scan-based Built-in Self Test (BIST) have limitations due to performance and area overhead as well as abnormal power consumption caused by the application of non-functional patterns. Moreover, integration of Design-for-Testability (DfT) circuitry into SoC architecture brings with it a need to resolve various complex timing issues related to multiple clock domains, multiple frequencies, and test-clock skews which are unique in the test mode. These traditional techniques could slow down the time-to-market of a new SoC design.; In this dissertation, we propose embedded software-based self-testing techniques which reuse the on-chip resources for self-test. In this methodology, the programmable cores are used for on-chip test generation, measurement, response analysis, and even diagnosis. After the programmable cores have been self-tested, they are reused for testing on-chip buses, interfaces and other non-programmable cores. The advantages of this methodology include at-speed testing, low hardware overhead, and application of functional patterns. In this dissertation, we discuss the details of the proposed techniques as well as the roadmap we are following and the challenges we are facing in developing the embedded software-based self-testing paradigm. |
