Design of energy efficient SOC with PIM architecture and deep submicron circuit techniques

The rapid advances in ultradeep submicron (UDSM) technology provide opportunities to monolithically integrate millions of gates and heterogeneous components to build a system-on-a-chip (SOC) for high performance and low power consumption. Particularly, integrating processors and memory on the same chip, called processor-in-memory (PIM) architecture, has an important effect on computer architecture. For successful SOC design, careful consideration should be taken into at all design levels from architectural to device in order to achieve design goals. In this work, we design and implement FlexRAM, a high-performance hybrid PIM architecture capable of serial and parallel execution. The energy efficient floor plan and memory hierarchy/configuration are designed. Techniques to control instantaneous peak and average power and operate FlexRAM efficiently with minimum performance penalty are developed and evaluated in an energy-delay matrix. An adaptively reconfigurable cache architecture with variable block prefetching and associativity are also designed to achieve high energy efficiency for different applications. Data sense amplifiers to overcome increased resistance and capacitance due to the longer signal line are designed. A built-in self-test (BIST) methodology with two-level linear-feedback shift-register (LFSR) and asynchronous test pattern transfer (ATPT) schemes for higher fault coverage and test time reduction is developed.; To tackle problems such as tremendously increased leakage current and power consumption due to the scaled threshold voltage of the transistor and increased number of gates in future VLSI chips, sub-1-V circuit techniques to suppress leakage current while meeting performance requirement are developed. High efficient charge recycling logic using charge sharing in the precharge cycle with no pre-evaluation problems and using ac power clocks with bootstrapped NMOS transistors are designed to reduce active power consumption further.